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参数资料
| 型号： | I5104XY |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | 音频合成 |
| 英文描述： | 262.2 SEC, SPEECH SYNTHESIZER WITH RCDG, UUC25 |
| 封装： | DIE-25 |
| 文件页数： | 34/87页 |
| 文件大小： | 616K |
| 代理商： | I5104XY |
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40
8393B-MCU Wireless-02/13
ATmega256/128/64RFR2
active processes, and forces an immediate transition to TRX_OFF. In contrast a
TRX_OFF command is stored until an active state (receiving or transmitting) has been
finished. After that the transition to TRX_OFF is performed.
For a fast transition from receive or active transmit states to PLL_ON state the
command FORCE_PLL_ON is provided. In contrast to FORCE_TRX_OFF this
command does not disable the PLL and the analog voltage regulator AVREG. It is not
available in states SLEEP, and RESET.
The completion of each requested state-change shall always be confirmed by reading
the bits TRX_STATUS of register TRX_STATUS.
9.4.1.2 Basic Operating Mode Description
9.4.1.2.1 SLEEP – Sleep State
In radio transceiver SLEEP state, the entire radio transceiver is disabled. No circuitry is
operating. The radio transceiver’s current consumption is reduced to leakage current
only. This state can only be entered from state TRX_OFF, by setting the bit
SLPTR = “1”.
Setting SLPTR = “0” returns the radio transceiver to the TRX_OFF state. During radio
transceiver SLEEP the register contents remains valid while the content of the Frame
Buffer and the security engine (AES) are cleared.
TRXRST = “1” in SLEEP state returns the radio transceiver to TRX_OFF state and
thereby sets all registers to their reset values.
9.4.1.2.2 TRX_OFF – Clock State
This state is reached immediately after Power On or Reset. In TRX_OFF the crystal
oscillator is running. The digital voltage regulator is enabled, thus the radio transceiver
registers, the Frame Buffer and security engine (AES) are accessible (see section
SLPTR and TRXRST in register TRXPR can be used for state control (see "State
Control" on page 39 for details). The analog front-end is disabled during TRX_OFF.
Entering the TRX_OFF state from radio transceiver SLEEP, or RESET state is
indicated by the TRX24_AWAKE interrupt.
9.4.1.2.3 PLL_ON – PLL State
Entering the PLL_ON state from TRX_OFF state first enables the analog voltage
regulator (AVREG). After the voltage regulator has been settled the PLL frequency
synthesizer is enabled. When the PLL has been settled at the receive frequency to a
channel defined by bits CHANNEL of register PHY_CC_CCA a successful PLL lock is
indicated by issuing a TRX24_PLL_LOCK interrupt.
If an RX_ON command is issued in PLL_ON state, the receiver is immediately enabled.
If the PLL has not been settled before the state change nevertheless takes place. Even
if the register bits TRX_STATUS of register TRX_STATUS indicates RX_ON, actual
frame reception can only start once the PLL has locked.
The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4.
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