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| 型号： | I5104XY |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | 音频合成 |
| 英文描述： | 262.2 SEC, SPEECH SYNTHESIZER WITH RCDG, UUC25 |
| 封装： | DIE-25 |
| 文件页数： | 86/87页 |
| 文件大小： | 616K |
| 代理商： | I5104XY |
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8393B-MCU Wireless-02/13
ATmega256/128/64RFR2
necessary for a robust oscillation during stable operation. This also keeps the drive
level of the crystal low.
Crystals with a higher load capacitance are generally less sensitive to parasitic pulling
effects caused by variations of external components or board and circuit parasitics. On
the other hand a larger crystal load capacitance results in a longer start-up time and a
higher steady state current consumption.
9.6.5.3 External Reference Frequency Setup
When using an external reference frequency, the signal must be connected to
pin XTAL1 as indicated in Figure 9-27 below and the bits XTAL_MODE of register
XOSC_CTRL need to be set to the external oscillator mode. The oscillation peak-to-
peak amplitude shall between 100 mV and 500 mV, the optimum range is between
400 mV and 500 mV. Pin XTAL2 should not be wired
Figure 9-27. Setup for Using an External Frequency Reference
XTAL2
XTAL1
IC internal
PCB
16 MHz
9.6.6 Frequency Synthesizer (PLL)
The main features of the phase-locked loop are:
Generate RX/TX frequencies for all 2.4 GHz channels of IEEE 802.15.4;
Autonomous calibration loops for stable operation within the operating range;
Two PLL-interrupts for status indication;
Fast PLL settling to support frequency hopping;
9.6.6.1 Overview
The PLL generates the RF frequencies for the radio transceiver. During receive
operation the frequency synthesizer works as a local oscillator for the receive frequency
of the radio transceiver. During transmit operation the voltage-controlled oscillator
(VCO) is directly modulated to generate the RF transmit signal. The frequency
synthesizer is implemented as a fractional-N PLL.
Two calibration loops ensure correct PLL functionality within the specified operating
limits.
9.6.6.2 Frequency Agility
When the PLL is enabled during state transition from TRX_OFF to PLL_ON the settling
time is typically tTR4 = 110 s including the settling time of the analog voltage regulator
(AVREG) and the PLL self calibration (refer to Table 9-9 on page 46Table 9-9). A lock
of the PLL is indicated with a TRX24_PLL_LOCK interrupt.
Switching between 2.4 GHz ISM band channels in PLL_ON or RX_ON states is
typically done within tTR20 = 11 s. This makes the radio transceiver highly suitable for
frequency hopping applications.
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