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| 型号： | I5104XY |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | 音频合成 |
| 英文描述： | 262.2 SEC, SPEECH SYNTHESIZER WITH RCDG, UUC25 |
| 封装： | DIE-25 |
| 文件页数： | 57/87页 |
| 文件大小： | 616K |
| 代理商： | I5104XY |
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61
8393B-MCU Wireless-02/13
ATmega256/128/64RFR2
configured by a short address and pan ID. The IEEE 64 bit address is the same for
every filter block.
There are some separate configuration bits for every filter block (see Table 9-13 below).
Table 9-13. Additional register set for Multiple Address Filter
Register Name
Description
{MAFSA0H,MAFSA0L}
short address for filter #0
both register are mirror register of
{SHORT_ADDR_1,SHORT_ADDR_0}
{MAFSA1H,MAFSA1L}
short address for filter #1
{MAFSA2H,MAFSA2L}
short address for filter #2
{MAFSA3H,MAFSA3L}
short address for filter #3
{MAFPA0H,MAFPA0L}
Pan ID for filter #0
both register are mirror register of
{PAN_ID_1,PAN_ID_0}
{MAFPA1H,MAFPA1L}
Pan ID for filter #1
{MAFPA2H,MAFPA2L}
Pan ID for filter #2
{MAFPA3H,MAFPA3L}
Pan ID for filter #3
MAFCR0
bits MAFxEN to enable filter #x
MAFCR1
bits AACK_I_AM_COORDx to enable filter #x as coordinator
bits AACK_SET_PDx to enable pending data bit of filter #x
TRX24_AMIx
each address filter #x generates the respective TRX24_AMIx
interrupt
Note: There are some register which are mirrored.
MAFSA0H <--> SHORT_ADDR_0
MAFSA1H <--> SHORT_ADDR_1
MAFPA0H <--> PAN_ID_0
MAFPA1H <--> PAN_ID_1
bit AACK_I_AM_COORD (register CSMA_SEED_1) <-->
bit AACK_I_AM_COORD0 (register MAFCR1)
bit AACK_SET_PD (register CSMA_SEED_1) <-->
bit AACK_SET_PD (register MAFCR1)
That means access to the registers is equal, the internal function can be written or read by both
registers.
Bit MAF0EN is set by reset to provide backward compatibility. The four address filter
blocks generate four address match interrupts.
Table 9-14. Additional AMI Interrupts for Multiple Address Filter
Interrupt Name
Description
TRX24_AMI0
address match interrupt from address filter #0, enabled bit AMI0 in
register IRQ_MASK1 is set
TRX24_AMI1
address match interrupt from address filter #1, enabled bit AMI1 in
register IRQ_MASK1 is set
TRX24_AMI2
address match interrupt from address filter #2, enabled bit AMI2 in
register IRQ_MASK1 is set
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