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参数资料
| 型号： | IDT72T18105L10BB |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 14/55页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 131X18 2.5V 10NS 24BGA |
| 标准包装： | 1 |
| 系列： | 72T |
| 功能： | 异步，同步 |
| 存储容量： | 2.3K（131 x 18） |
| 数据速率： | 10MHz |
| 访问时间： | 10ns |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 240-BGA |
| 供应商设备封装： | 240-PBGA（19x19） |
| 包装： | 托盘 |
| 其它名称： | 72T18105L10BB |
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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programming of
PAEandPAFvaluescanbeachievedbyusingacombination
of the
LD,SEN,SCLKandSIinputpins.ProgrammingPAEandPAFproceeds
asfollows:when
LDandSENaresetLOW,dataontheSIinputarewritten,one
bit for each SCLK rising edge, starting with the Empty Offset LSB and ending
with the Full Offset MSB. If x9 to x9 mode is selected, a total of 24 bits for the
IDT72T1845, 26 bits for the IDT72T1855, 28 bits for the IDT72T1865, 30 bits
for the IDT72T1875, 32 bits for the IDT72T1885, 34 bits for the IDT72T1895,
36 bits for the IDT72T18105, 38 bits for the IDT72T18115 and 40 bits for the
IDT72T18125. For any other mode of operation (that includes x18 bus width
on either the Input or Output), minus 2 bits from the values above. So, a total
of 22 bits for the IDT72T1845, 24 bits for the IDT72T1855, 26 bits for the
IDT72T1865, 28 bits for the IDT72T1875, 30 bits for the IDT72T1885, 32 bits
for the IDT72T1895, 34 bits for the IDT72T18105, 36 bits for the IDT72T18115
and 38 bits for the IDT72T18125. See Figure 20, Serial Loading of Program-
mable Flag Registers, for the timing diagram for this mode.
Using the serial method, individual registers cannot be programmed
selectively.
PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programmingsequence. Inthiscase,theprogrammingofalloffsetbitsdoesnot
have to occur at once. A select number of bits can be written to the SI input and
then, by bringing
LD and SEN HIGH, data can be written to FIFO memory via
Dn by toggling
WEN. WhenWEN is brought HIGH with LD and SEN restored
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruptionofserialprogrammingisdesired,itissufficienteithertoset
LDLOW
and deactivate
SENortosetSENLOWanddeactivateLD. OnceLDandSEN
are both restored to a LOW level, serial offset programming continues.
From the time serial programming has begun, neither programmable flag
will be valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising SCLK edge that achieves the above criteria;
PAFwillbevalidafterthreemorerisingWCLKedgesplustPAF,PAEwillbevalid
after the next three rising RCLK edges plus tPAE.
ItisonlypossibletoreadtheflagoffsetvaluesviatheparalleloutputportQn.
PARALLEL MODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then
programming of
PAEandPAFvaluescanbeachievedbyusingacombination
of the
LD,WCLK,WENandDninputpins.IftheFIFOisconfiguredforaninput
bus width and output bus width both set to x9, then the total number of write
operations required to program the offset registers is 4 for the IDT72T1845/
72T1855/72T1865/72T1875/72T1885 or 6 for the IDT72T1895/72T18105/
72T18115/72T18125. Refer to Figure 3, Programmable Flag Offset Pro-
gramming Sequence,for a detailed diagram of the data input lines D0-Dnused
duringparallelprogramming.IftheFIFOisconfiguredforaninputtooutputbus
width of x9 to x18, x18 to x9 or x18 to x18, then the following number of write
operationsarerequired.Foraninputbuswidthofx18atotalof2writeoperations
will be required to program the offset registers for the IDT72T1845/72T1855/
72T1865/72T1875/72T1885/72T1895 or 4 for the IDT72T18105/72T18115/
72T18125. For an input bus width of x9 a total of 4 write operations will be
requiredtoprogramtheoffsetregistersfortheIDT72T1845/72T1855/72T1865/
72T1875/72T1885.Atotalof6willberequiredfortheIDT72T1895/72T18105/
72T18115/72T18125. Refer to Figure 3, Programmable Flag Offset Pro-
gramming Sequence, for a detailed diagram.
For example, programming
PAEandPAFontheIDT72T1895configured
for x18 bus width proceeds as follows: when
LD and WEN are set LOW, data
ontheinputsDnarewrittenintotheLSBoftheEmptyOffsetRegisteronthefirst
LOW-to-HIGH transition of WCLK. Upon the second LOW-to-HIGH transition
ofWCLK,dataarewrittenintotheMSBoftheEmptyOffsetRegister.Onthethird
LOW-to-HIGHtransitionofWCLK,dataarewrittenintotheLSBoftheFullOffset
Register. On the fourth LOW-to-HIGH transition of WCLK, data are written into
theMSBoftheFullOffsetRegister.ThefifthLOW-to-HIGHtransitionofWCLK,
data are written, once again to the Empty Offset Register. Note that for x9 bus
width, one extra Write cycle is required for both the Empty Offset Register and
Full Offset Register. See Figure 21, Parallel Loading of Programmable Flag
Registers, for the timing diagram for this mode.
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programmingsequence.Inthiscase,theprogrammingofalloffsetregistersdoes
not have to occur at one time. One, two or more offset registers can be written
and then by bringing
LDHIGH,writeoperationscanberedirectedtotheFIFO
memory. When
LDissetLOWagain,andWENisLOW,thenextoffsetregister
in sequence is written to. As an alternative to holding
WEN LOWandtoggling
LD, parallel programming can also be interrupted by setting LD LOW and
toggling
WEN.
Note that the status of a programmable flag (
PAEor PAF)outputisinvalid
during the programming process. From the time parallel programming has
begun, a programmable flag output will not be valid until the appropriate offset
word has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria;
PAF will be valid after
twomorerisingWCLKedgesplustPAF,
PAEwillbevalidafterthenexttworising
RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0-Qn
pins when
LD is set LOW and REN is set LOW. It is important to note that
consecutivereadsoftheoffsetregistersisnotpermitted.Thereadoperationmust
be disabled for a minimum of one RCLK cycle in between offset register
accesses. If the FIFO is configured for an input bus width and output bus width
bothsettox9,thenthetotalnumberofreadoperationsrequiredtoreadtheoffset
registers is 4 for the IDT72T1845/72T1855/72T1865/72T1875/72T1885 or 6
for the IDT72T1895/72T18105/72T18115/72T18125. Refer to Figure 3,
Programmable Flag Offset Programming Sequence, for a detailed diagram
of the data input lines D0-Dn used during parallel programming. If the FIFO is
configured for an input to output bus width of x9 to x18, x18 to x9 or x18 to x18,
then the following number of read operations are required: for an output bus
widthofx18atotalof2readoperationswillberequiredtoreadtheoffsetregisters
for the IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895 or 4 for
the IDT72T18105/72T18115/72T18125. For an output bus width of x9 a total
of 4 read operations will be required to read the offset registers for the
IDT72T1845/72T1855/72T1865/72T1875/72T1885. A total of 6 will be re-
quired for the IDT72T1895/72T18105/72T18115/72T18125. Refer to Figure
3,ProgrammableFlagOffsetProgrammingSequence,foradetaileddiagram.
See Figure 22, Parallel Read of Programmable Flag Registers, for the timing
diagram for this mode.
It is permissible to interrupt the offset register read sequence with reads or
writes to the FIFO. The interruption is accomplished by deasserting
REN,LD,
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| IDT72T18105L4-4BB | 功能描述:IC FIFO 131X18 2.5V 4NS 240BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T18105L4-4BBG | 功能描述:IC FIFO 131072X18 SYNC 240BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T18105L5BB | 功能描述:IC FIFO 131X18 2.5V 5NS 240BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T18105L5BBGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 131X18 2.5V 5NS 240BGA |
| IDT72T18105L5BBI | 功能描述:IC FIFO 131X18 2.5V 5NS 240BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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