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| 型号： | IDT72T18105L10BB |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 50/55页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 131X18 2.5V 10NS 24BGA |
| 标准包装： | 1 |
| 系列： | 72T |
| 功能： | 异步，同步 |
| 存储容量： | 2.3K（131 x 18） |
| 数据速率： | 10MHz |
| 访问时间： | 10ns |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 240-BGA |
| 供应商设备封装： | 240-PBGA（19x19） |
| 包装： | 托盘 |
| 其它名称： | 72T18105L10BB |
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54
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72T1845 can easily be adapted to applications requiring depths
greaterthan2,048whenthex18Inputorx18OutputbusWidthisselected,4,096
for the IDT72T1855, 8,192 for the IDT72T1865, 16,384 for the IDT72T1875,
32,768 for the IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the
IDT72T18105, 262,144 for the IDT72T18115 and 524,288 for the
IDT72T18125. When both x9 Input and x9 Output bus Widths are selected,
depths greater than 4,096 can be adapted for the IDT72T1845, 8,192 for the
IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the IDT72T1875,
65,536 for the IDT72T1885, 131,072 for the IDT72T1895, 262,144 for the
IDT72T8105, 524,288 for the IDT72T18115 and 1,048,576 for the
IDT72T18125.InFWFTmode,theFIFOscanbeconnectedinseries(thedata
outputs of one FIFO connected to the data inputs of the next) with no external
logic necessary. The resulting configuration provides a total depth equivalent
to the sum of the depths associated with each single FIFO. Figure 37 shows
a depth expansion using two IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895/72T18105/72T18115/72T18125 devices.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain – no read operation is
necessarybuttheRCLKofeachFIFOmustbefree-running. Eachtimethedata
word appears at the outputs of one FIFO, that device's
OR line goes LOW,
enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for
ORof
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
whereNisthenumberofFIFOsintheexpansionandTRCLKistheRCLKperiod.
Note that extra cycles should be added for the possibility that the tSKEW1
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock, for the
OR flag.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFO of the chain, that FIFO's
IRlinegoesLOW,enablingtheprecedingFIFO
to write a word to fill it.
Forafullexpansionconfiguration,theamountoftimeittakesfor
IRofthefirst
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock, for the
IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
end of the chain and free locations to the beginning of the chain.
Figure 37. Block Diagram of Depth Expansion
For the x18 Input or x18 Output bus Width:
4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18, 131,072 x 18, 262,144 x 18, 524,288 x 18 and 1,048,576 x 18
For both x9 Input and x9 Output bus Widths:
8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9, 131,072 x 9, 262,144 x 9, 524,288 x 9, 1,048,576 x 9 and 2,097,152 x 9
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
TRANSFER CLOCK
5909 drw41
n
FWFT/SI
IDT
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
RCS
READ CHIP SELECT
RCS
IDT
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
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| IDT72T18105L4-4BB | 功能描述:IC FIFO 131X18 2.5V 4NS 240BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T18105L4-4BBG | 功能描述:IC FIFO 131072X18 SYNC 240BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T18105L5BB | 功能描述:IC FIFO 131X18 2.5V 5NS 240BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T18105L5BBGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 131X18 2.5V 5NS 240BGA |
| IDT72T18105L5BBI | 功能描述:IC FIFO 131X18 2.5V 5NS 240BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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