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参数资料
| 型号： | IDT72T18105L10BB |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 16/55页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 131X18 2.5V 10NS 24BGA |
| 标准包装： | 1 |
| 系列： | 72T |
| 功能： | 异步，同步 |
| 存储容量： | 2.3K（131 x 18） |
| 数据速率： | 10MHz |
| 访问时间： | 10ns |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 240-BGA |
| 供应商设备封装： | 240-PBGA（19x19） |
| 包装： | 托盘 |
| 其它名称： | 72T18105L10BB |
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23
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
SIGNAL DESCRIPTION
INPUTS:
DATA IN (D0 - Dn)
Data inputs for 18-bit wide data (D0 - D17) or data inputs for 9-bit wide data
(D0 - D8).
CONTROLS:
MASTER RESET (
MRS )
AMasterResetisaccomplishedwheneverthe
MRSinputistakentoaLOW
state.Thisoperationsetstheinternalreadandwritepointerstothefirstlocation
of the RAM array.
PAE will go LOW, PAF willgo HIGH, and HF willgoHIGH.
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
along with
EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT/SI is HIGH, then the First Word Fall Through mode (FWFT), along with
IR and OR, are selected. OR will go HIGH and IR will go LOW.
AllcontrolsettingssuchasOW,IW,
BE,RM,PFMandIParedefinedduring
the Master Reset cycle.
DuringaMasterReset,theoutputregisterisinitializedtoallzeroes.AMaster
Reset is required after power up, before a write operation can take place.
MRS
is asynchronous.
See Figure 9, Master Reset Timing, for the relevant timing diagram.
PARTIAL RESET (
PRS)
APartialResetisaccomplishedwheneverthe
PRS inputistakentoaLOW
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array,
PAEgoesLOW, PAFgoesHIGH,
and
HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
or First Word Fall Through, that mode will remain selected. If the IDT Standard
mode is active, then
FF will go HIGH and EF will go LOW. If the First Word
Fall Through mode is active, then
OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently active at
the time of Partial Reset is also retained. The output register is initialized to all
zeroes.
PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation,whenreprogrammingprogrammableflagoffsetsettingsmaynotbe
convenient.
See Figure 10, Partial Reset Timing, for the relevant timing diagram.
ASYNCHRONOUS WRITE (
ASYW)
The write port can be configured for either Synchronous or Asynchronous
mode of operation. If during Master Reset the
ASYW input is LOW, then
Asynchronous operation of the write port will be selected. During Asynchro-
nous operation of the write port the WCLK input becomes WR input, this is the
Asynchronous write strobe input. A rising edge on WR will write data present
on the Dn inputs into the FIFO. (
WEN must be tied LOW when using the write
port in Asynchronous mode).
When the write port is configured for Asynchronous operation the full flag
(
FF)operatesinanasynchronousmanner,thatis,thefullflagwillbeupdated
based in both a write operation and read operation. Note, if Asynchronous
mode is selected, FWFT is not permissable. Refer to Figures 30, 31, 34 and
35 for relevant timing and operational waveforms.
ASYNCHRONOUS READ (
ASYR)
The read port can be configured for either Synchronous or Asynchronous
mode of operation. If during a Master Reset the
ASYR input is LOW, then
Asynchronous operation of the read port will be selected. During Asynchro-
nous operation of the read port the RCLK input becomes RD input, this is the
Asynchronous read strobe input. A rising edge on RD will read data from the
FIFO via the output register and Qn port. (
REN must be tied LOW during
Asynchronous operation of the read port).
The
OE input provides three-state control of the Qn output bus, in an
asynchronous manner. (
RCS,providesthree-statecontrolofthereadportin
Synchronous mode).
When the read port is configured for Asynchronous operation the device
must be operating on IDT standard mode, FWFT mode is not permissible if the
readportisAsynchronous.TheEmptyFlag(
EF)operatesinanAsynchronous
manner, that is, the empty flag will be updated based on both a read operation
and a write operation. Refer to Figures 32, 33, 34 and 35 for relevant timing
and operational waveforms.
RETRANSMIT (
RT)
The Retransmit (
RT) input is used in conjunction with the MARK input,
together they provide a means by which data previously read out of the FIFO
can be reread any number of times. If retransmit operation has been selected
(i.e.theMARKinputisHIGH),arisingedgeonRCLKwhile
RTisLOWwillreset
thereadpointerbacktothememorylocationsetbytheuserviatheMARKinput.
IfIDTstandardmodehasbeenselectedthe
EFflagwillgoLOWandremain
LOW for the time that
RT is held LOW. RT can be held LOW for any number
of RCLK cycles, the read pointer being reset to the marked location. The next
rising edge of RCLK after
RT has returned HIGH, will cause EF to go HIGH,
allowingreadoperationstobeperformedontheFIFO.Thenextreadoperation
will access data from the ‘marked’ memory location.
Subsequent retransmit operations may be performed, each time the read
pointerreturningtothe‘marked’location.SeeFigure18,RetransmitfromMark
(IDT Standard mode) for the relevant timing diagram.
IfFWFTmodehasbeenselectedthe
ORflagwillgoHIGHandremainHIGH
for the time that
RTisheldLOW.RTcanbeheldLOWforanynumberofRCLK
cycles, the read pointer being reset to the ‘marked’ location. The next RCLK
rising edge after
RT has returned HIGH, will cause OR to go LOW and due to
FWFToperation,thecontentsofthemarkedmemorylocationwillbeloadedonto
the output register, a read operation being required for all subsequent data
reads.
Subsequent retransmit operations may be performed each time the read
pointerreturningtothe‘marked’location.SeeFigure19,RetransmitfromMark
(FWFT mode) for the relevant timing diagram.
MARK
The MARK input is used to select Retransmit mode of operation. An RCLK
rising edge while MARK is HIGH will mark the memory location of the data
currently present on the output register, the device will also be placed into
retransmit mode. Note, for the IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895 there must be a minimum of 32 bytes of data between the
writepointerandreadpointerwhentheMARKisasserted,fortheIDT72T18105/
72T18115 there must be a minimum of 128 bytes and for the IDT72T18125
there must be a minimum of 256 bytes. Remember, 2(x9) bytes = 1(x18) word.
(32 bytes = 16 word = 8 long words). Also, once the MARK is set, the write
pointer will not increment past the “marked” location until the MARK is
deasserted. This prevents “overwriting” of retransmit data.
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| IDT72T18105L4-4BB | 功能描述:IC FIFO 131X18 2.5V 4NS 240BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T18105L4-4BBG | 功能描述:IC FIFO 131072X18 SYNC 240BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T18105L5BB | 功能描述:IC FIFO 131X18 2.5V 5NS 240BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T18105L5BBGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 131X18 2.5V 5NS 240BGA |
| IDT72T18105L5BBI | 功能描述:IC FIFO 131X18 2.5V 5NS 240BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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