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| 型号： | IDT72T18105L10BB |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 18/55页 |
| 文件大小： | 0K |
| 描述： | IC FIFO 131X18 2.5V 10NS 24BGA |
| 标准包装： | 1 |
| 系列： | 72T |
| 功能： | 异步，同步 |
| 存储容量： | 2.3K（131 x 18） |
| 数据速率： | 10MHz |
| 访问时间： | 10ns |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 240-BGA |
| 供应商设备封装： | 240-PBGA（19x19） |
| 包装： | 托盘 |
| 其它名称： | 72T18105L10BB |
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25
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FEBRUARY 10, 2009
OUTPUT ENABLE (
OE)
When Output Enable is enabled (LOW), the parallel output buffers receive
datafromtheoutputregister. When
OEisHIGH,theoutputdatabus(Qn)goes
intoahighimpedancestate.DuringMasteroraPartialResetthe
OEistheonly
inputthatcanplacetheoutputbusQn,intoHigh-Impedance.DuringResetthe
RCS input can be HIGH or LOW, it has no effect on the Qn outputs.
READ CHIP SELECT (
RCS )
The Read Chip Select input provides synchronous control of the Read
output port. When
RCS goes LOW, the next rising edge of RCLK causes the
QnoutputstogototheLow-Impedancestate. When
RCSgoesHIGH,thenext
RCLK rising edge causes the Qn outputs to return to HIGH Z. During a Master
orPartialResetthe
RCSinputhasnoeffectontheQnoutputbus,OEistheonly
inputthatprovidesHigh-ImpedancecontroloftheQnoutputs.If
OEisLOWthe
Qn data outputs will be Low-Impedance regardless of
RCSuntilthefirstrising
edge of RCLK after a Reset is complete. Then if
RCSisHIGHthedataoutputs
will go to High-Impedance.
The
RCSinputdoesnoteffecttheoperationoftheflags. Forexample,when
the first word is written to an empty FIFO, the
EFwillstillgofromLOWtoHIGH
based on a rising edge of RCLK, regardless of the state of the
RCS input.
Also, when operating the FIFO in FWFT mode the first word written to an
empty FIFO will still be clocked through to the output register based on RCLK,
regardless of the state of
RCS. For this reason the user must take care when
adatawordiswrittentoanemptyFIFOinFWFTmode.If
RCSisdisabledwhen
anemptyFIFOiswritteninto,thefirstwordwillfallthroughtotheoutputregister,
but will not be available on the Qn outputs which are in HIGH-Z. The user must
take
RCSactiveLOWtoaccessthisfirstword,placetheoutputbusinLOW-Z.
RENmustremaindisabledHIGHforatleastonecycleafterRCShasgoneLOW.
A rising edge of RCLK with
RCS and REN active LOW, will read out the next
word. Care must be taken so as not to lose the first word written to an empty
FIFO when
RCSis HIGH. Refer to Figure 17,RCS andREN ReadOperation
(FWFT Mode). The
RCS pin must also be active (LOW) in order to perform
aRetransmit. SeeFigure13forReadCycleandReadChipSelectTiming(IDT
Standard Mode). See Figure 16 for Read Cycle and Read Chip Select Timing
(First Word Fall Through Mode).
If Asynchronous operation of the Read port has been selected, then
RCS
must be held active, (tied LOW).
OE provides three-state control of Qn.
WRITE PORT HSTL SELECT (WHSTL)
Thecontrolinputs,datainputsandflagoutputsassociatedwiththewriteport
can be setup to be either HSTL or LVTTL. If WHSTL is HIGH during the Master
Reset,thenHSTLoperationofthewriteportwillbeselected.IfWHSTLisLOW
at Master Reset, then LVTTL will be selected.
The inputs and outputs associated with the write port are listed in Table 5.
READ PORT HSTL SELECT (RHSTL)
Thecontrolinputs,datainputsandflagoutputsassociatedwiththereadport
can be setup to be either HSTL or LVTTL. If RHSTL is HIGH during the Master
Reset, then HSTL operation of the read port will be selected. If RHSTL is LOW
at Master Reset, then LVTTL will be selected for the read port, then echo clock
and echo read enable will not be provided.
The inputs and outputs associated with the read port are listed in Table 5.
SYSTEM HSTL SELECT (SHSTL)
Allinputsnotassociatedwiththewriteandreadportcanbesetuptobeeither
HSTL or LVTTL. If SHSTL is HIGH during Master Reset, then HSTL operation
of all the inputs not associated with the write and read port will be selected. If
SHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs
associated with SHSTL are listed in Table 5.
LOAD (
LD)
This is a dual purpose pin. During Master Reset, the state of the
LD input,
alongwithFSEL0andFSEL1,determinesoneofeightdefaultoffsetvaluesfor
the
PAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisters
can be programmed, parallel or serial (see Table 2). After Master Reset,
LD
enables write operations to and read operations from the offset registers. Only
theoffsetloadingmethodcurrentlyselectedcanbeusedtowritetotheregisters.
Offset registers can be read only in parallel.
AfterMasterReset,the
LDpinisusedtoactivatetheprogrammingprocess
oftheflagoffsetvalues
PAEandPAF.PullingLDLOWwillbeginaserialloading
or parallel load or read of these offset values. THIS PIN MUST BE HIGH
AFTER MASTER RESET TO WRITE OR READ DATA TO/FROM THE FIFO
MEMORY.
BUS-MATCHING (IW, OW)
The pins IW and OW are used to define the input and output bus widths.
DuringMasterReset,thestateofthesepinsisusedtoconfigurethedevicebus
sizes. See Table 1 for control settings. All flags will operate on the word/byte
size boundary as defined by the selection of bus width. See Figure 5 for Bus-
Matching Byte Arrangement.
BIG-ENDIAN/LITTLE-ENDIAN (
BE)
During Master Reset, a LOW on
BE will select Big-Endian operation. A
HIGH on
BEduringMasterResetwillselectLittle-Endianformat.Thisfunction
is useful when data is written into the FIFO in word format (x18) and read out
of the FIFO in word format (x18) or byte format (x9). If Big-Endian mode is
selected, then the most significant byte of the word written into the FIFO will be
read out of the FIFO first, followed by the least significant byte. If Little-Endian
formatisselected,thentheleastsignificantbyteofthewordwrittenintotheFIFO
will be read out first, followed by the most significant byte. The mode desired
is configured during master reset by the state of the Big-Endian (
BE)pin.See
Figure 5 for Bus-Matching Byte Arrangement.
PROGRAMMABLE FLAG MODE (PFM)
During Master Reset, a LOW on PFM will select Asynchronous Program-
mable flag timing mode. A HIGH on PFM will select Synchronous Program-
mable flag timing mode. If asynchronous
PAF/PAE configuration is selected
(PFM, LOW during
MRS), the PAE is asserted LOW on the LOW-to-HIGH
transition of RCLK.
PAE is reset to HIGH on the LOW-to-HIGH transition of
WCLK. Similarly, the
PAFisassertedLOWontheLOW-to-HIGHtransitionof
WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.
If synchronous
PAE/PAF configuration is selected (PFM, HIGH during
MRS) , the
PAE isassertedandupdatedontherisingedgeofRCLKonlyand
notWCLK.Similarly,
PAFisassertedandupdatedontherisingedgeofWCLK
only and not RCLK. The mode desired is configured during master reset by
the state of the Programmable Flag Mode (PFM) pin.
INTERSPERSED PARITY (IP)
During Master Reset, a LOW on IP will select Non-Interspersed Parity
mode. A HIGH will select Interspersed Parity mode. The IP bit function allows
the user to select the parity bit in the word loaded into the parallel port (D0-Dn)
whenprogrammingtheflagoffsets.IfInterspersedParitymodeisselected,then
theFIFOwillassumethattheparitybitislocatedinbitpositionD8andD17during
the parallel programming of the flag offsets, and will therefore ignore D8 when
loading the offset register in parallel mode. This is also applied to the output
register when reading the value of the offset register. If Interspersed Parity is
selected then output Q8 will be invalid. If Non-Interspersed Parity mode is
selected, then D16 and D17 are the parity bits and are ignored during parallel
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| IDT72T18105L4-4BB | 功能描述:IC FIFO 131X18 2.5V 4NS 240BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T18105L4-4BBG | 功能描述:IC FIFO 131072X18 SYNC 240BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T18105L5BB | 功能描述:IC FIFO 131X18 2.5V 5NS 240BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| IDT72T18105L5BBGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 131X18 2.5V 5NS 240BGA |
| IDT72T18105L5BBI | 功能描述:IC FIFO 131X18 2.5V 5NS 240BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72T 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
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