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参数资料
| 型号： | IDT821054PQFG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/45页 |
| 文件大小： | 0K |
| 描述： | IC PCM CODEC QUAD MPI 64-PQFP |
| 标准包装： | 84 |
| 类型： | PCM 编解码器/滤波器 |
| 数据接口： | PCM 音频接口 |
| ADC / DAC 数量： | 4 / 4 |
| 三角积分调变： | 无 |
| 电压 - 电源，模拟： | 4.75 V ~ 5.25 V |
| 电压 - 电源，数字： | 4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-QFP |
| 供应商设备封装： | 64-PQFP（14x14） |
| 包装： | 管件 |
| 其它名称： | 800-2516-5 821054PQFG IDT821054PQFG-ND |
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10
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
2.1.2
PCM BUS
The IDT821054 provides two flexible PCM buses for all 4 channels.
The digital PCM data can be compressed (A/-law) or linear code. As
shown in Figure - 3, the data rate can be configured as same as the Bit
Clock (BCLK) or half of it. The PCM data is transmitted or received
either on the rising edges or on the falling edges of the BCLK signal. The
transmit and receive time slots can offset from the FS signal by 0 to 7
periods of BCLK. All these configurations are made by global register
GREG7, which is effective for all four channels.
The PCM data of each channel can be assigned to any time slot of
the PCM bus. The number of available time slots is determined by the
frequency of the BCLK signal. For example, if the frequency is 512 kHz,
8 time slots (TS0 to TS7) are available. If the frequency is 1.024 MHz,
16 time slots (TS0 to TS15) are available. The IDT821054 accepts
BCLK frequency of 512 kHz to 8.192 MHz at increments of 64 kHz.
When compressed PCM code (8-bit wide) is selected, the voice data
of one channel occupies one time slot. The TT[6:0] bits in local register
LREG5 select the transmit time slot for each channel, while the RT[6:0]
bits in LREG6 select the receive time slot for each channel.
When linear PCM code is selected, the voice data is a 16-bit 2’s
complement number (b13 to b0 are effective bits, b15 and b14 are as
same as the sign bit b13). So, the voice data of one channel occupies
one time slot group, which consists of 2 adjacent time slots. The TT[6:0]
bits in LREG5 select a transmit time slot group for the specified channel.
If TT[6:0] = n(d), it means that time slots TS(2n+1) and TS(2n+2) are
selected. For example, if TT[6:0] = 00H, it means that TS0 and TS1 are
selected. The RT[6:0] bits in LREG6 select a receive time slot group for
the specified channel in the same way.
The PCM data of each individual channel can be clocked out to
transmit PCM highway one (DX1) or two (DX2) on the programmed
edges of BCLK according to time slot assignment. The transmit PCM
highway is selected by the THS bit in LREG5. The frame sync (FS)
pulse identifies the beginning of a transmit frame (TS0). The PCM data
is serially transmitted on DX1 or DX2 with MSB first.
The PCM data of each individual channel is received from receive
PCM highway one (DR1) or two (DR2) on the programmed edges of
BCLK according to time slot assignment. The receive PCM highway is
selected by the RHS bit in LREG6. The frame sync (FS) pulse identifies
the beginning of a receive frame (TS0). The PCM data is serially
received from DR1 or DR2 with MSB first.
Figure - 3 Sampling Edge Selection Waveform
Bit 7
TS0
FS
BCLK
Single Clock
Transmit
Receive
BCLK
Double Clock
PCM Clock Slope Bits
in GREG7:
CS = 000
CS = 001
CS = 010
CS = 011
CS = 100
CS = 101
CS = 110
CS = 111
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相关代理商/技术参数 |
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| IDT821064 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE |
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