- 您现在的位置：买卖IC网 > PDF目录10950 > IDT821054PQFG (IDT, Integrated Device Technology Inc)IC PCM CODEC QUAD MPI 64-PQFP PDF资料下载
参数资料
| 型号： | IDT821054PQFG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 25/45页 |
| 文件大小： | 0K |
| 描述： | IC PCM CODEC QUAD MPI 64-PQFP |
| 标准包装： | 84 |
| 类型： | PCM 编解码器/滤波器 |
| 数据接口： | PCM 音频接口 |
| ADC / DAC 数量： | 4 / 4 |
| 三角积分调变： | 无 |
| 电压 - 电源，模拟： | 4.75 V ~ 5.25 V |
| 电压 - 电源，数字： | 4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-QFP |
| 供应商设备封装： | 64-PQFP（14x14） |
| 包装： | 管件 |
| 其它名称： | 800-2516-5 821054PQFG IDT821054PQFG-ND |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页当前第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页
31
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
3.4.3
LOCAL REGISTERS LIST
LREG1: Coefficient Selection, Read/Write (00H/80H)
The Coefficient Select bits (CS[7:0]) are used to control digital filters and function blocks on each channel. The digital filters include
Impedance Matching Filter, Echo Cancellation Filter, High-Pass Filter, Gain for Impedance Scaling, Gain in the Transmit/Receive Path
and Frequency Response Correction in the Transmit/Receive Path. See Figure - 4 on page 11 for details. It should be noted that the
Impedance Matching Filter and Gain for Impedance Scaling are working together to adjust the impedance. So the CS[0] and CS[2] bits
should be set to the same value to ensure proper operation.
CS [7] = 0: The Digital Gain Filter in the Receive path (GRX) is disabled (default);
CS [7] = 1: The Digital Gain in the Receive path (GRX) is programmed by the Coe-RAM.
CS [6] = 0: The Frequency Response Correction filter in the Receive path (FRR) is disabled (default);
CS [6] = 1: The coefficient of the Frequency Response Correction filter in the Receive path (FRR) is programmed by the Coe-RAM.
CS [5] = 0: The Digital Gain Filter in the Transmit path (GTX) is disabled (default);
CS [5] = 1: The Digital Gain in the Transmit path (GTX) is set by the Coe-RAM.
CS [4] = 0: The Frequency Response Correction filter in the Transmit path (FRX) is disabled (default);
CS [4] = 1: The coefficient of the Frequency Response Correction filter in the Transmit path (FRX) is programmed by the Coe-RAM.
CS [3] = 0: The High-Pass Filter (HPF) is bypassed/disabled;
CS [3] = 1: The High-Pass Filter (HPF) is enabled (default).
CS [2] = 0: The Gain for Impedance Scaling filter (GIS) is disabled (default);
CS [2] = 1: The coefficient of the Gain for Impedance Scaling filter (GIS) is programmed by the Coe-RAM.
CS [1] = 0: The Echo Cancellation Filter (ECF) is disabled (default);
CS [1] = 1: The coefficient of the Echo Cancellation Filter (ECF) is programmed by the Coe-RAM.
CS [0] = 0: The Impedance Matching Filter (IMF) is disabled (default);
CS [0] = 1: The coefficient of theImpedance Matching Filter (IMF) is programmed by the Coe-RAM.
LREG2: Local Loopback Control and SLIC Input Interrupt Enable, Read/Write (01H/81H)
The SLIC Input Interrupt Enable bits IE[4:0] enable or disable the interrupt signal on each channel.
IE[4] = 0: Interrupt disabled. The interrupt generated by changes of SB3 (when SB3 is selected as an input) will be ignored (default);
IE[4] = 1: Interrupt enabled. The interrupt generated by changes of SB3 (when SB3 is selected as an input) will be recognized.
IE[3] = 0: Interrupt disabled. The interrupt generated by changes of SB2 (when SB2 is selected as an input) will be ignored (default);
IE[3] = 1: Interrupt enabled. The interrupt generated by changes of SB2 (when SB2 is selected as an input) will be recognized.
IE[2] = 0: Interrupt disabled. The interrupt generated by changes of SB1 (when SB1 is selected as an input) will be ignored (default);
IE[2] = 1: Interrupt enabled. The interrupt generated by changes of SB1 (when SB1 is selected as an input) will be recognized.
IE[1] = 0: Interrupt disabled. The interrupt generated by changes of SI2 will be ignored (default);
IE[1] = 1: Interrupt enabled. The interrupt generated by changes of SI2 will be recognized.
IE[0] = 0: Interrupt disabled. The interrupt generated by changes of SI1 will be ignored (default);
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
0000
00
I/O data
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
0000
01
I/O data
IE[4]
IE[3]
IE[2]
IE[1]
IE[0]
DLB_PCM
ALB_1BIT
DLB_1BIT
相关PDF资料 |
PDF描述 |
|---|---|
| MCIMX357CVM5BR2 | IC MPU I.MX35 400MAPBGA |
| MCIMX357CVM5B | IC MPU I.MX35 400MAPBGA |
| MCIMX357CJQ5CR2 | MULTIMEDIA PROCESSOR 400-MAPBGA |
| MCF5270CVM150J | IC MCU 32BIT 150MHZ 196-MAPBGA |
| ADV202BBCZ-150 | IC VIDEO CODEC JPEG2000 144CSBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT821064 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE |
| IDT821064PQF | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE |
| IDT821068 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:OCTAL PROGRAMMABLE PCM CODEC |
| IDT821068PX | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:OCTAL PROGRAMMABLE PCM CODEC |
| IDT821621 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:LONG HAUL SLIC |
发布紧急采购，3分钟左右您将得到回复。