参数资料
型号: IDT821054PQFG
厂商: IDT, Integrated Device Technology Inc
文件页数: 24/45页
文件大小: 0K
描述: IC PCM CODEC QUAD MPI 64-PQFP
标准包装: 84
类型: PCM 编解码器/滤波器
数据接口: PCM 音频接口
ADC / DAC 数量: 4 / 4
三角积分调变:
电压 - 电源,模拟: 4.75 V ~ 5.25 V
电压 - 电源,数字: 4.75 V ~ 5.25 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-QFP
供应商设备封装: 64-PQFP(14x14)
包装: 管件
其它名称: 800-2516-5
821054PQFG
IDT821054PQFG-ND
30
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
The Linear/Compressed bit (L/C) determines the mode of level meter operation.
L/C = 0:
Message mode is selected. The compressed PCM data will be output to GREG19 transparently (default).
L/C = 1:
Metering mode is selected. The linear PCM data will be metered and the result will be output to the registers
GREG18 and GREG19.
The Level Meter Channel Select bits (CS[1:0]) select a channel, data on which will be level metered.
CS[1:0] = 00:
Channel 1 is selected (default);
CS[1:0] = 01:
Channel 2 is selected;
CS[1:0] = 10:
Channel 3 is selected;
CS[1:0] = 11:
Channel 4 is selected.
GREG22: Global Loopback Control and PLL Power Down, Read/Write (35H/B5H)
The PLL Power Down bit (PPD) controls the operation state of the PLL block.
PPD = 0:
The PLL is disabled. The device is in normal operation state (default);
PPD = 1:
The PLL is powered down. The device works in power-saving mode. All clocks stop running.
The Loop Control bits determine the loopback status. Refer to Figure - 4 on page 11 for detailed information.
DLB_ANA = 0:
The Digital Loopback via Analog Interface is disabled (default);
DLB_ANA = 1:
The Digital Loopback via Analog Interface is enabled.
ALB_8k = 0:
The Analog Loopback via 8 kHz Interface is disabled (default);
ALB_8k = 1:
The Analog Loopback via 8 kHz Interface is enabled.
DLB_8k = 0:
The Digital Loopback via 8 kHz Interface is disabled (default);
DLB_8k = 1:
The Digital Loopback via 8 kHz Interface is enabled.
DLB_DI = 0:
The Digital Loopback from DR to DX is disabled (default);
DLB_DI = 1:
The Digital Loopback from DR to DX is enabled.
ALB_DI = 0:
The Analog Loopback from DX to DR is disabled (default);
ALB_DI = 1:
The Analog Loopback from DX to DR is enabled.
GREG23: Over-sampling Timing Tuning, Read/Write (37H/B7H)
To improve the performance of total distortion, it is recommended to write a data byte of 40H to this register. The default value is 00H.
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
1101
01
I/O data
Reserved
PPD
DLB_ANA
ALB_8k
DLB_8k
DLB_DI
ALB_DI
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
1101
11
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