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参数资料
| 型号： | IDT821054PQFG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 28/45页 |
| 文件大小： | 0K |
| 描述： | IC PCM CODEC QUAD MPI 64-PQFP |
| 标准包装： | 84 |
| 类型： | PCM 编解码器/滤波器 |
| 数据接口： | PCM 音频接口 |
| ADC / DAC 数量： | 4 / 4 |
| 三角积分调变： | 无 |
| 电压 - 电源，模拟： | 4.75 V ~ 5.25 V |
| 电压 - 电源，数字： | 4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-QFP |
| 供应商设备封装： | 64-PQFP（14x14） |
| 包装： | 管件 |
| 其它名称： | 800-2516-5 821054PQFG IDT821054PQFG-ND |
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34
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
transmit PCM data. For compressed code (A/-Law), this register is not used (when being read, it will output a data byte of 00H).
The high byte of transmit PCM data will be read out by applying a read command to this register, and at the same time, it will be
transmitted to the PCM highway without any interference.
LREG9: A/D Gain, D/A Gain, Channel Power Down and PCM Receive Path Cutoff, Read/Write (08H/88H)
The Channel Power Down bit (PD) selects the operation mode for the corresponding channel:
PD = 0:
The corresponding channel is in normal operation state;
PD = 1:
The corresponding channel is powered down (default).
The PCMCT bit determines the operation of PCM Receive Path of the corresponding channel:
PCMCT = 0:
The PCM Receive Path of the corresponding channel is in normal operation state (default);
PCMCT = 1:
The PCM Receive Path of the corresponding channel is cut off.
The A/D Gain bit (GAD) sets the gain of analog A/D for the corresponding channel:
GAD = 0:
0 dB (default);
GAD = 1:
+6 dB.
The D/A Gain bit (GDA) sets the gain of analog D/A for the corresponding channel:
GDA = 0:
0 dB (default);
GDA = 1:
-6 dB.
Attention: To ensure proper operation, the lower 4 bits of the I/O data byte following the write command (88H) must be '0000'.
LREG10: Tone Generator Enable, Read/Write (09H/89H)
TEN1 = 0:
Tone generator 1 is disabled (default);
TEN1 = 1:
Tone generator 1 is enabled.
TEN0 = 0:
Tone generator 0 is disabled (default);
TEN0 = 1:
Tone generator 0 is enabled.
Attention: To ensure proper operation, the b3 and b2 of the I/O data byte following the write command (89H) must be ‘11’.
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
0010
00
I/O data
PD
PCMCT
GAD
GDA
0
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
0010
01
I/O data
Reserved
1
TEN1
TEN0
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相关代理商/技术参数 |
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| IDT821064 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE |
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