参数资料
型号: IDT821054PQFG
厂商: IDT, Integrated Device Technology Inc
文件页数: 20/45页
文件大小: 0K
描述: IC PCM CODEC QUAD MPI 64-PQFP
标准包装: 84
类型: PCM 编解码器/滤波器
数据接口: PCM 音频接口
ADC / DAC 数量: 4 / 4
三角积分调变:
电压 - 电源,模拟: 4.75 V ~ 5.25 V
电压 - 电源,数字: 4.75 V ~ 5.25 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-QFP
供应商设备封装: 64-PQFP(14x14)
包装: 管件
其它名称: 800-2516-5
821054PQFG
IDT821054PQFG-ND
27
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
GREG10: SB1 Direction Control and SB1 Status/Control Data, Read/Write (29H/A9H)
The SB1 direction control bits SB1C[3:0] in this register determine the directions of the SB1 pins of Channel 4 to Channel 1 respectively.
SB1C[0] = 0:
the SB1 pin of Channel 1 is configured as input (default);
SB1C[0] = 1:
the SB1 pin of Channel 1 is configured as output;
SB1C[1] = 0:
the SB1 pin of Channel 2 is configured as input (default);
SB1C[1] = 1:
the SB1 pin of Channel 2 is configured as output;
SB1C[2] = 0:
the SB1 pin of Channel 3 is configured as input (default);
SB1C[2] = 1:
the SB1 pin of Channel 3 is configured as output;
SB1C[3] = 0:
the SB1 pin of Channel 4 is configured as input (default);
SB1C[3] = 1:
the SB1 pin of Channel 4 is configured as output.
When the SB1 pins of Channel 1 to Channel 4 are configured as inputs, the SB1[0] to SB1[3] bits contain the status of these four SB1
pins respectively. When the SB1 pins of Channel 1 to Channel 4 are configured as outputs, the control data is written to these four SB1
pins via the SB1[0] to SB1[3] bits respectively.
GREG11: SB2 Direction Control and SB2 Status/Control Data, Read/Write (2AH/AAH)
The SB2 direction control bits SB2C[3:0] in this register determine the directions of the SB2 pins of Channel 4 to Channel 1 respectively.
SB2C[0] = 0:
the SB2 pin of Channel 1 is configured as input (default);
SB2C[0] = 1:
the SB2 pin of Channel 1 is configured as output;
SB2C[1] = 0:
the SB2 pin of Channel 2 is configured as input (default);
SB2C[1] = 1:
the SB2 pin of Channel 2 is configured as output;
SB2C[2] = 0:
the SB2 pin of Channel 3 is configured as input (default);
SB2C[2] = 1:
the SB2 pin of Channel 3 is configured as output;
SB2C[3] = 0:
the SB2 pin of Channel 4 is configured as input (default);
SB2C[3] = 1:
the SB2 pin of Channel 4 is configured as output.
When the SB2 pins of Channel 1 to Channel 4 are configured as inputs, the SB2[0] to SB2[3] bits contain the status of these four SB2
pins respectively. When the SB2 pins of Channel 1 to Channel 4 are configured as outputs, the control data is written to these four SB2
pins via the SB2[0] to SB2[3] bits respectively.
GREG12: SB3 Direction Control and SB3 Status/Control Data, Read/Write (2BH/ABH)
The SB3 direction control bits SB3C[3:0] in this register determine the directions of the SB3 pins of Channel 4 to Channel 1 respectively.
SB3C[0] = 0:
the SB3 pin of Channel 1 is configured as input (default);
SB3C[0] = 1:
the SB3 pin of Channel 1 is configured as output;
SB3C[1] = 0:
the SB3 pin of Channel 2 is configured as input (default);
SB3C[1] = 1:
the SB3 pin of Channel 2 is configured as output;
SB3C[2] = 0:
the SB3 pin of Channel 3 is configured as input (default);
SB3C[2] = 1:
the SB3 pin of Channel 3 is configured as output;
SB3C[3] = 0:
the SB3 pin of Channel 4 is configured as input (default);
SB3C[3] = 1:
the SB3 pin of Channel 4 is configured as output.
When the SB3 pins of Channel 1 to Channel 4 are configured as inputs, the SB3[0] to SB3[3] bits contain the status of these four SB3
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
1010
01
I/O data
SB1C[3]
SB1C[2]
SB1C[1]
SB1C[0]
SB1[3]
SB1[2]
SB1[1]
SB1[0]
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
1010
10
I/O data
SB2C[3]
SB2C[2]
SB2C[1]
SB2C[0]
SB2[3]
SB2[2]
SB2[1]
SB2[0]
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
1010
11
I/O data
SB3C[3]
SB3C[2]
SB3C[1]
SB3C[0]
SB3[3]
SB3[2]
SB3[1]
SB3[0]
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