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| 型号： | IDT821054PQFG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 9/45页 |
| 文件大小： | 0K |
| 描述： | IC PCM CODEC QUAD MPI 64-PQFP |
| 标准包装： | 84 |
| 类型： | PCM 编解码器/滤波器 |
| 数据接口： | PCM 音频接口 |
| ADC / DAC 数量： | 4 / 4 |
| 三角积分调变： | 无 |
| 电压 - 电源，模拟： | 4.75 V ~ 5.25 V |
| 电压 - 电源，数字： | 4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-QFP |
| 供应商设备封装： | 64-PQFP（14x14） |
| 包装： | 管件 |
| 其它名称： | 800-2516-5 821054PQFG IDT821054PQFG-ND |
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17
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
3
OPERATING THE IDT821054
3.1
PROGRAMMING DESCRIPTION
The IDT821054 is programmed by writing commands to registers
and coefficient RAM. A Channel Program Enable register (GREG6) is
provided for addressing individual or multiple channels. The CE[3:0] bits
in this register are assigned to Channel 4 to Channel 1 respectively. The
channels are enabled to be programmed by setting their respective CE
bits to ‘1’. If two or more channels are enabled, the successive write
commands will be effective to all enabled channels. A broadcast mode
can be implemented by simply enabling all four channels before
performing other write-operation. The broadcast mode is very useful for
configuring the coefficient RAM of the IDT821054 in a large system. But
for read operations, multiple addressing is not allowed.
The IDT821054 uses an Identification Code to distinguish itself from
other devices in the system. When being read, the IDT821054 will
output an Identification Code of 81H first to indicate that the following
data bytes are from the IDT821054.
3.1.1
COMMAND TYPE AND FORMAT
The IDT821054 provides three types of commands as follows:
Local Command (LC), which is used to address the local registers of
the specified channel(s).
Global Command (GC), which is used to address the global registers
of all four channels.
RAM Command (RC), which is used to address the coefficient RAM
(Coe-RAM) and FSK-RAM.
The format of the command is as the following:
R/W:
Read/Write Command bit
b7 = 0:
Read Command
b7 = 1:
Write Command
CT:
Command Type
b6 b5 = 00: LC - Local Command
b6 b5 = 01: GC - Global Command
b6 b5 = 10: Not Allowed
b6 b5 = 11: RC - RAM Command
Address: b[4:0], specify one or more local/global registers or a block
of Coe-RAM or FSK-RAM to be addressed.
For Local Command and Global Command, the b[4:0] bits are used
to specify the address of the local registers and global registers
respectively.
For the RAM Command, b4 is used to distinguish the Coe-RAM and
the FSK-RAM:
b4 = 0:
Command for addressing the Coe-RAM. The b[3:0] bits
are used to address the blocks in the Coe-RAM.
b4 = 1:
Command for addressing the FSK-RAM. The b3 bit is
always ‘0’ and the b[2:0] bits are used to address the blocks in the FSK-
RAM.
3.1.2
ADDRESSING THE LOCAL REGISTERS
When addressing the local registers, users must specify which
channel(s) will be addressed first. If two or more channels are specified
via GREG6, the corresponding local registers of the specified channels
will be addressed by a Local Command at the same time.
The IDT821054 provides a consecutive adjacent addressing method
for accessing the local registers. According to the address specified in a
Local Command, there will be 1 to 4 adjacent local registers to be
addressed automatically, with the highest order first. For example, if the
address specified in a Local Command ends with ‘11’ (b1b0 = 11), 4
adjacent registers will be addressed by this command; if b1b0 = 10, 3
adjacent registers will be addressed. See Table - 2 for details.
When addressing local registers, the procedure of consecutive
adjacent addressing can be stopped by the CS signal at any time. If CS
is changed from low to high, the operation to the current register and the
next adjacent registers will be aborted. However, the previous operation
results will not be affected.
3.1.3
ADDRESSING THE GLOBAL REGISTERS
For global registers are shared by all four channels, it is no need to
specify the channel(s) before addressing a global register. Except for
this, the global registers are addressed in a similar way as local
registers. The procedure of consecutive adjacent addressing can be
stopped by the CS signal at any time.
3.1.4
ADDRESSING THE COE-RAM
There are totally 40 words of Coe-RAM per channel. They are
divided to 5 blocks. Each block consists of 8 words. Each word is 14-bit
wide.
The 5 blocks of the Coe-RAM are assigned for different filter
coefficients as shown below (refer to “9 Appendix: IDT821054 Coe-RAM
Mapping” for the address of the Coe-RAM):
Block 1: IMF RAM (Word 0 - Word 7), containing the Impedance
Matching Filter coefficient.
Block 2: ECF RAM (Word 8 - Word 15), containing the Echo
Cancellation Filter coefficient.
Block 3: GIS RAM (Word 16 - Word 19) and Tone Generator RAM
(Word 20 - Word 23), containing the Gain of Impedance Scaling and
dual tone coefficients.
Block 4: FRX RAM (Word 24 - Word 30) and GTX RAM (Word 31),
containing the coefficient of the Frequency Response Correction in
Transmit Path and the Gain in Transmit Path;
b7
b6
b5
b4
b3
b2
b1
b0
R/W
CT
Address
Table - 2 Consecutive Adjacent Addressing
Address Specified in a Local
Command
In/Out Data
Bytes
Address of the Local
Registers to be accessed
b[4:0] = XXX11
(b1b0 = 11, four bytes of data)
byte 1
XXX11
byte 2
XXX10
byte 3
XXX01
byte 4
XXX00
b[4:0] = XXX10
(b1b0 = 10, three bytes of data)
byte 1
XXX10
byte 2
XXX01
byte 3
XXX00
b[4:0] = XXX01
(b1b0 = 01, two bytes of data)
byte 1
XXX01
byte 2
XXX00
b[4:0] = XXX00
(b1b0 = 00, one byte of data)
byte 1
XXX00
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