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参数资料
| 型号： | IDT821054PQFG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 22/45页 |
| 文件大小： | 0K |
| 描述： | IC PCM CODEC QUAD MPI 64-PQFP |
| 标准包装： | 84 |
| 类型： | PCM 编解码器/滤波器 |
| 数据接口： | PCM 音频接口 |
| ADC / DAC 数量： | 4 / 4 |
| 三角积分调变： | 无 |
| 电压 - 电源，模拟： | 4.75 V ~ 5.25 V |
| 电压 - 电源，数字： | 4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-QFP |
| 供应商设备封装： | 64-PQFP（14x14） |
| 包装： | 管件 |
| 其它名称： | 800-2516-5 821054PQFG IDT821054PQFG-ND |
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IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
FO = 1:
The FSK function block is enabled.
The BT/Bellcore Select bit (BS) determines which specification the IDT821054 will follow:
BS = 0:
Bellcore specification is selected (default);
BS = 1:
BT specification is selected.
The Mark After Send bit (MAS) determines if the FSK generator will keep on sending a mark-after-send signal (a stream of ‘1’) after
sending out all data in the FSK-RAM.
MAS = 0:
The output will be muted after all data in the FSK-RAM has been sent out (default);
MAS = 1:
The FSK generator keeps on sending out a mark-after-send signal after sending out all data in the FSK-RAM.
If the MAS bit is set to ‘0’ and the FS bit is set to ‘1’, the mark-after-send signal will be stopped.
The FSK Start bit (FS) should be set to ‘1’ to start sending FSK signal. It will be automatically reset after all data in the FSK-RAM has
been sent out. If the Seizure Length, Mark Length and Data Length are set to 0, the FS bit will be reset to ‘0’ immediately after it is set to
‘1’.
FS = 0:
FSK transmission is disabled (default);
FS = 1:
FSK transmission starts.
GREG18: Level Meter Result Low Byte, Read Only (31H)
This register contains the low byte of the level meter result. The default value is 00H.
The LVLL[0] bit in this register will be set to ‘1’ when the level meter result (both high and low bytes) is ready, and it will be reset to ‘0’
immediately after the high byte of result is read. To read the level meter result, it is recommended to the low byte first, then read the high
byte (LVLH[7:0] in GREG19).
GREG19: Level Meter Result High Byte, Read Only (32H)
This register contains the high byte of the level meter result. The default value is 00H.
GREG20: Level Meter Count Number, Read/Write (33H/B3H)
The CN[7:0] bits are used to set the number of time cycles for sampling the PCM data.
CN[7:0] = 0 (d):
the PCM data is output to the result registers GREG18 and GREG19 directly;
CN[7:0] = N (d):
the PCM data is sampled for N
× 125 s (N is from 1 to 255).
GREG21: Level Meter Channel and Linear/Compressed Mode Selection, Level Meter On/Off, Read/Write (34H/B4H)
The Level Meter On/Off bit (LMO) enables/disables the level meter.
LMO = 0:
The level meter is disabled (default);
LMO = 1:
The level meter is enabled.
b7
b6
b5
b4
b3
b2
b1
b0
Command
00
1100
01
I/O data
LVLL[7]
LVLL[6]
LVLL[5]
LVLL[4]
LVLL[3]
LVLL[2]
LVLL[1]
LVLL[0]
b7
b6
b5
b4
b3
b2
b1
b0
Command
00
1100
10
I/O data
LVLH[7]
LVLH[6]
LVLH[5]
LVLH[4]
LVLH[3]
LVLH[2]
LVLH[1]
LVLH[0]
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
1100
11
I/O data
CN[7]
CN[6]
CN[5]
CN[4]
CN[3]
CN[2]
CN[1]
CN[0]
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
1101
00
I/O data
Reserved
LMO
L/C
CS[1]
CS[0]
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