参数资料
型号: IS42VS16160D-75BLI
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: DRAM
英文描述: 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54
封装: 13 X 8 MM, 0.80 MM PITCH, LEAD FREE, MS-207, BGA-54
文件页数: 44/61页
文件大小: 939K
代理商: IS42VS16160D-75BLI
Integrated Silicon Solution, Inc. — www.issi.com
49
Rev. 00A
04/21/09
IS42VS83200D, IS42VS16160D
IS45VS83200D, IS45VS16160D
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0
T1
T2
T3
T4
T5
T6
T7
NOP
DOUT a
DOUT a+1
DOUT b
DOUT b+1
BANK n,
COL a
CAS Latency - 3 (BANK n)
CAS Latency - 3 (BANK m)
tRP - BANK n
tRP -BANKm
READ - AP
BANK n
READ - AP
BANK m
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
Idle
Page Active
READ with Burst of 4
Precharge
Internal States
BANK n,
COL b
BURST READ/SINGLE WRITE
Theburstread/singlewritemodeisenteredbyprogramming
the write burst mode bit (M9) in the mode register to a logic
1. In this mode, all WRITE commands result in the access
ofasinglecolumnlocation(burstofone),regardlessof
theprogrammedburstlength.READcommandsaccess
columns according to the programmed burst length and
sequence,justasinthenormalmodeofoperation(M9
=0).
CONCURRENT AUTO PRECHARGE
Anaccesscommand(READorWRITE)toanotherbank
while an access command with auto precharge enabled is
executingisnotallowedbySDRAMs,unlesstheSDRAM
supports CONCURRENT AUTO PRECHARGE.
ISSI
SDRAMssupportCONCURRENTAUTOPRECHARGE.
FourcaseswhereCONCURRENTAUTOPRECHARGE
occurs are defined below.
READ with Auto Precharge
1.InterruptedbyaREAD(withorwithoutautoprecharge):
AREADtobankmwillinterruptaREADonbankn,
CAS latency later.The PRECHARGE to bank n will
beginwhentheREADtobankmisregistered.
2.InterruptedbyaWRITE(withorwithoutautoprecharge):
AWRITEtobankmwillinterruptaREADonbankn
whenregistered.DQMshouldbeusedthreeclocksprior
totheWRITEcommandtopreventbuscontention.The
PRECHARGEtobanknwillbeginwhentheWRITEto
bank m is registered.
READ With Auto Precharge interrupted by a READ
READ With Auto Precharge interrupted by a WRITE
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQM
DQ
T0
T1
T2
T3
T4
T5
T6
T7
NOP
DOUT a
DIN b
DIN b+1
DIN b+2
DIN b+3
BANK n,
COL a
BANK m,
COL b
CAS Latency - 3 (BANK n)
tRP - BANK n
tDPL -BANKm
READ - AP
BANK n
WRITE - AP
BANK m
READ with Burst of 4
Interrupt Burst, Precharge
Idle
Page Active
WRITE with Burst of 4
Write-Back
Internal States Page Active
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