参数资料
型号: IS42VS16160D-75BLI
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: DRAM
英文描述: 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54
封装: 13 X 8 MM, 0.80 MM PITCH, LEAD FREE, MS-207, BGA-54
文件页数: 46/61页
文件大小: 939K
代理商: IS42VS16160D-75BLI
50
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
04/21/09
IS42VS83200D, IS42VS16160D
IS45VS83200D, IS45VS16160D
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0
T1
T2
T3
T4
T5
T6
T7
NOP
DIN a
DIN a+1
DOUT b
DOUT b+1
BANK n,
COL a
BANK m,
COL b
CAS Latency - 3 (BANK m)
tRP - BANK n
tRP -BANKm
WRITE - AP
BANK n
READ - AP
BANK m
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
Page Active
READ with Burst of 4
Precharge
Internal States
tDPL - BANK n
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0
T1
T2
T3
T4
T5
T6
T7
NOP
BANK n,
COL a
BANK m,
COL b
tRP - BANK n
tDPL -BANKm
WRITE - AP
BANK n
WRITE - AP
BANK m
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
Page Active
WRITE with Burst of 4
Write-Back
Internal States
tDPL - BANK n
DIN a
DIN a+1
DIN a+2
DIN b
DIN b+1
DIN b+2
DIN b+3
WRITE with Auto Precharge
3.InterruptedbyaREAD(withorwithoutautoprecharge):
AREADtobankmwillinterruptaWRITEonbanknwhen
registered, with the data-out appearing (CAS latency)
later.ThePRECHARGEtobanknwillbeginaftertdpl
is met, where tdplbeginswhentheREADtobankmis
registered.ThelastvalidWRITE to bank n will be data-in
registeredoneclockpriortotheREADtobankm.
4.InterruptedbyaWRITE(withorwithoutautoprecharge):
AWRITE to bank m will interrupt a WRITE on bank n when
registered.ThePRECHARGEtobanknwillbeginafter
tdpl is met, where tdplbeginswhentheWRITEtobank
misregistered.ThelastvaliddataWRITEtobankn
willbedataregisteredoneclockpriortoaWRITEto
bank m.
WRITE With Auto Precharge interrupted by a READ
WRITE With Auto Precharge interrupted by a WRITE
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