参数资料
| 型号： | ISL6267HRZ |
| 厂商： | Intersil |
| 文件页数： | 14/33页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR MULTIPHASE 48TQFN |
| 标准包装： | 50 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.013 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 管件 |
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ISL6267
Theory of Operation
Multiphase R 3 ? Modulator
out-of-phase. If VR1 is in 1-phase mode, the master clock signal
will be distributed to Phase 1 only and be the Clock1 signal.
The ISL6267 is a multiphase regulator implementing two voltage
regulators, V DD and VDDNB, on one chip controlled by AMD’s?
SVI1? protocol. V DD can be programmed for 1-, 2- or 3-phase
operation. VDDNB can be configured for 1-phase or 2-phase
operation. Both regulators use the Intersil patented R 3 ? (Robust
Ripple Regulator) modulator. The R 3 ? modulator combines the
best features of fixed frequency PWM and hysteretic PWM while
eliminating many of their shortcomings. Figure 7 conceptually
shows the multiphase R 3 ? modulator circuit, and Figure 8 shows
the operation principles.
VW
VCRM
COMP
MASTER
CLOCK
CLOCK1
PWM1
HYSTERETIC
WINDOW
VW
MASTER CLOCK CIRCUIT
MASTER
CLOCK2
MASTER
CLOCK
COMP
VCRM
CLOCK
PHASE
SEQUENCER
CLOCK1
CLOCK2
CLOCK3
PWM2
GMVO
CRM
SLAVE CIRCUIT 1
CLOCK3
VW
CLOCK1
S
R
Q
PWM1
PHASE1
L1
I L1
VO
CO
PWM3
VW
VCRS1
GM
CRS1
VCRS2
VCRS3
VCRS1
SLAVE CIRCUIT 2
VW
CLOCK2
S
R
Q
PWM2
PHASE2
L2
I L2
FIGURE 8. R 3 ? MODULATOR OPERATION PRINCIPLES IN
STEADY STATE
CRS2
VCRS2
GM
Each slave circuit has its own ripple capacitor C rs , whose voltage
mimics the inductor ripple current. A g m amplifier converts the
inductor voltage into a current source to charge and discharge
CRS3
VW
VCRS3
CLOCK3
GM
SLAVE CIRCUIT 3
S PWM3
Q
R
PHASE3
L3
I L3
C rs . The slave circuit turns on its PWM pulse upon receiving the
clock signal, and the current source charges C rs . When C rs
voltage V Crs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges C rs .
Since the controller works with V crs , which are large amplitude
and noise-free synthesized signals, it achieves lower phase jitter
than conventional hysteretic mode and fixed PWM mode
FIGURE 7. R 3 ? MODULATOR CIRCUIT
A current source flows from the VW pin to the COMP pin, creating
a voltage window set by the resistor between the two pins. This
voltage window is called “VW window” in the following
discussion.
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor C rm with a current source equal
to g m V o , where g m is a gain factor. C rm voltage V CRM is a
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP, and generates a
one-shot master clock signal. A phase sequencer distributes the
master clock signal to the slave circuits. If V DD is in 3-phase
mode, the master clock signal is distributed to the three phases,
and the Clock 1~3 signals will be 120° out-of-phase. If VR1 is in
2-phase mode, the master clock signal is distributed to Phases 1
and 2, and the Clock1 and Clock2 signals will be 180°
14
controllers. Unlike conventional hysteretic mode converters, the
error amplifier allows the ISL6267 to maintain a 0.5% output
voltage accuracy.
Figure 9 shows the operation principles during load insertion
response. The COMP voltage rises during load insertion,
generating the master clock signal more quickly, so the PWM
pulses turn on earlier, increasing the effective switching
frequency. This allows for higher control loop bandwidth than
conventional fixed frequency PWM controllers. The VW voltage
rises as the COMP voltage rises, making the PWM pulses wider.
During load release response, the COMP voltage falls. It takes
the master clock circuit longer to generate the next master clock
signal so the PWM pulse is held off until needed. The VW voltage
falls as the COMP voltage falls, reducing the current PWM pulse
width. This kind of behavior gives the ISL6267 excellent response
speed.
The fact that all the phases share the same VW window voltage
also ensures excellent dynamic current balance among phases.
January 8, 2013
FN7801.1
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| ISL6267HRZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLR FOR AMD FUSION UP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6268 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:High-Performance Notebook PWM Controller |
| ISL6268CAZ | 功能描述:IC REG CTRLR BUCK PWM 16-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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