参数资料
| 型号： | ISL6267HRZ |
| 厂商： | Intersil |
| 文件页数： | 17/33页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR MULTIPHASE 48TQFN |
| 标准包装： | 50 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.013 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 管件 |
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ISL6267
SVC
TABLE 1. PRE-PWROK METAL VID CODES
OUTPUT VOLTAGE
SVD (V)
If the PWROK input is de-asserted, then the controller steps both
the Core and the Northbridge VRs back to the stored pre-PWROK
metal VID level in the holding register from initial soft-start. No
attempt is made to read the SVC and SVD inputs during this time.
0
0
1
1
0
1
0
1
1.1
1.0
0.9
0.8
If PWROK is re-asserted, then the on-board SVI interface waits for
a set VID command.
If ENABLE goes low during normal operation, all internal drivers
are tri-stated and PGOOD is pulled low. This event clears the
pre-PWROK metal VID code and forces the controller to check
The internal DAC circuitry begins to ramp Core and Northbridge
VRs to the decoded pre-PWROK Metal VID output level. The
digital soft-start circuitry ramps the internal reference to the
target gradually at a fixed rate of approximately 2mV/μs. The
controlled ramp of all output voltage planes reduces in-rush
current during the soft-start interval. At the end of the soft-start
interval, the PGOOD output transitions high, indicating all output
planes are within regulation limits.
If the ENABLE input falls below the enable falling threshold, the
ISL6267 tri-states both outputs. PGOOD is pulled low with the
loss of ENABLE. The Core and Northbridge planes decay, based
on output capacitance and load leakage resistance. If bias to V CC
falls below the POR level, the ISL6267 responds in the manner
previously described. Once V CC and ENABLE rise above their
respective rising thresholds, the internal DAC circuitry reacquires
a pre-PWROK metal VID code, and the controller soft-starts.
VFIX Mode
The ISL6267 does not support VFIX Mode. In the event a CPU is
not present on a motherboard and the ISL6267 is powered on,
the state of SVC and SVD sets the pre-PWROK metal VID as the
SVI Mode
Once the controller has successfully soft-starts and PGOOD and
PGOOD_NB transition high, the processor can assert PWROK to
signal the ISL6267 to prepare for SVI commands. The controller
actively monitors the SVI interface for set VID commands to
move the plane voltages to start-up VID values. Details of the SVI
Bus protocol are provided in the “AMD Design Guide for Voltage
Regulator Controllers Accepting Serial VID Codes” specification.
Once a set VID command is received, the ISL6267 decodes the
information to determine which VR is affected and which VID
target is required (see Table 2). The internal DAC circuitry steps
the output voltage of the VR commanded to the new VID level.
During this time, one or more of the VR outputs could be
targeted. In the event either VR is commanded to power-off by
serial VID commands, the PGOOD signal remains asserted.
17
SVC and SVD upon restart.
A POR event on either VCC or VIN during normal operation shuts
down both regulators, and both PGOOD outputs are pulled low.
The pre-PWROK metal VID code is not retained.
VID-on-the-Fly Transition
Once PWROK is high, the ISL6267 detects this flag and begins
monitoring the SVC and SVD pins for SVI instructions. The
microprocessor follows the protocol outlined in the following
sections to send instructions for the VID-on-the-fly transitions.
The ISL6267 decodes the instruction and acknowledges the new
VID code. For the VID codes higher than the current VID level, the
ISL6267 begins stepping the commanded VR outputs to the new
VID target with a typical slew rate of 7.5mV/μs, which meets the
AMD requirements.
When the VID codes are lower than the current VID level, the
ISL6267 checks the state of PSI_L. If PSI_L is high, the controller
begins stepping the regulator output to the new VID target with a
typical slew rate of -7.5mV/μs. If PSI_L is low, the controller
allows the output voltage to decay and slowly steps the DAC
down with the natural decay of the output. This allows the
controller to quickly recover and move to a high VID code if
commanded. AMD requirements under these conditions do not
require the regulator to meet the minimum slew rate
specification of -5mV/μs. In either case, the slew rate is not
allowed to exceed 10mV/μs. The ISL6267 does not change the
state of PGOOD (VCCPWRGD in AMD specifications), when a
VID-on-the-fly transition occurs.
SVI WIRE Protocol
The SVI WIRE protocol is based on the I 2 C bus concept. Two wires
[serial clock (SVC) and serial data (SVD)], carry information
between the AMD processor (master) and the VR controller
(slave) on the bus. The master initiates and terminates SVI
transactions and drives the clock, SVC, during a transaction. The
AMD processor is always the master, and the voltage regulators
are the slaves. The slave receives the SVI transactions and acts
accordingly. Mobile SVI WIRE protocol timing is based on
high-speed mode I 2 C. See AMD publication # 40182 for
additional details.
January 8, 2013
FN7801.1
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