参数资料
| 型号： | ISL6267HRZ |
| 厂商： | Intersil |
| 文件页数： | 15/33页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR MULTIPHASE 48TQFN |
| 标准包装： | 50 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.013 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 管件 |
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ISL6267
VW
COMP
PHASE
V CRM
UG ATE
MASTER
CLOCK
CLOCK1
PWM1
CLOCK2
PWM2
CLOCK3
LG ATE
IL
FIGURE 10. DIODE EMULATION
PWM3
VW
V CRS
IL
VW
CCM/DCM
BOUNDARY
VCRS1
VCRS3
VCRS2
FIGURE 9. R 3 ? MODULATOR OPERATION PRINCIPLES IN LOAD
INSERTION RESPONSE
V CRS
VW LIGHT DCM
Diode Emulation and Period Stretching
The ISL6267 can operate in diode emulation (DE) mode to
improve light-load efficiency. In DE mode, the low-side MOSFET
IL
V CRS
VW
DEEP DCM
conducts when the current is flowing from source to drain and
does not allow reverse current, thus emulating a diode. As
Figure 10 shows, when LGATE is on, the low-side MOSFET carries
current, creating negative voltage on the phase node due to the
voltage drop across the ON-resistance. The ISL6267 monitors the
current by monitoring the phase node voltage. It turns off LGATE
when the phase node voltage reaches zero to prevent the inductor
current from reversing the direction and creating unnecessary
power loss. If the load current is light enough, (see Figure 10). The
inductor current reaches and stays at zero before the next phase
node pulse, and the regulator is in discontinuous conduction
mode (DCM). If the load current is heavy enough, the inductor
current will never reaches 0A, and the regulator is in CCM,
although the controller is in DE mode.
Figure 11 shows the operation principle in diode emulation mode
at light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size and therefore is the same, making the inductor
current triangle the same in the three cases. The ISL6267 clamps
the ripple capacitor voltage V CRS in DE mode to make it mimic the
inductor current. It takes the COMP voltage longer to hit V CRS ,
naturally stretching the switching period. The inductor current
triangles move farther apart such that the inductor current
average value is equal to the load current. The reduced switching
frequency helps increase light-load efficiency.
15
IL
FIGURE 11. PERIOD STRETCHING
Start-up Timing
With the controller's V DD and V IN voltages above their POR
threshold, the start-up sequence begins when ENABLE exceeds the
logic high threshold. Figure 12 shows the typical start-up timing of
VR1 and VR2. The ISL6267 uses digital soft-start to rampup DAC
to the voltage programmed by the Metal VID. PGOOD is asserted
high and low at the end of the rampup. Similar results occur if
ENABLE is tied to V DD , with the soft-start sequence starting
800μs after V DD crosses the POR threshold.
January 8, 2013
FN7801.1
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