参数资料
| 型号： | ISL6267HRZ |
| 厂商： | Intersil |
| 文件页数： | 25/33页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR MULTIPHASE 48TQFN |
| 标准包装： | 50 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.013 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 管件 |
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ISL6267
C n = ------------------------------------------------------------
R ntcnet × --------------
----------------------------------------- × DCR
L
R sum
N
N
R sum
R ntcnet + --------------
(EQ. 23)
i o
i L
For example, given N = 3, R sum = 3.65k Ω , R p = 11k Ω ,
R ntcs = 2.61k Ω , R ntc = 10k Ω , DCR = 0.88m Ω and L = 0.36μH,
Equation 23 gives C n = 0.406μF.
Assuming the compensator design is correct, Figure 21 shows the
RING
BACK
Vo
expected load transient response waveforms if C n is correctly
selected. When the load current I core has a square change, the
output voltage V core also has a square response.
FIGURE 24. OUTPUT VOLTAGE RING-BACK PROBLEM
If C n value is too large or too small, V Cn (s) does not accurately
represent real-time I o (s) and worsens the transient response.
Figure 22 shows the load transient response when C n is too
small. V core sags excessively upon load insertion and may create
a system failure. Figure 23 shows the transient response when
C n is too large. V core is sluggish in drooping to its final value.
There is excessive overshoot if load insertion occurs during this
time, which may negatively affect the CPU reliability.
Rntcs
Rntc
Rp
Cn.1
Rn
OPTIONAL
ISUM+
Cn.2 Vcn
ISUM-
Ri
i o
Rip
Cip
OPTIONAL
Vo
FIGURE 21. DESIRED LOAD TRANSIENT RESPONSE
WAVEFORMS
i o
Vo
FIGURE 22. LOAD TRANSIENT RESPONSE WHEN C n IS TOO
SMALL
i o
Vo
FIGURE 23. LOAD TRANSIENT RESPONSE WHEN C n IS TOO
LARGE
25
FIGURE 25. OPTIONAL CIRCUITS FOR RING-BACK REDUCTION
Figure 24 shows the output voltage ring-back problem during
load transient response. The load current i o has a fast step
change, but the inductor current i L cannot accurately follow.
Instead, i L responds in first-order system fashion due to the
nature of the current loop. The ESR and ESL effect of the output
capacitors makes the output voltage V o dip quickly upon load
current change. However, the controller regulates V o according to
the droop current i droop , which is a real-time representation of i L ;
therefore, it pulls V o back to the level dictated by i L , causing the
ring-back problem. This phenomenon is not observed when the
output capacitor has very low ESR and ESL, as is the case with all
ceramic capacitors.
Figure 25 shows two optional circuits for reduction of the
ring-back. C n is the capacitor used to match the inductor time
constant. It usually takes the parallel of two (or more) capacitors
to get the desired value. Figure 25 shows that two capacitors
(C n.1 and C n.2 ) are in parallel. Resistor R n is an optional
component to reduce the V o ring-back. At steady state,
C n.1 + C n.2 provides the desired C n capacitance. At the beginning
of i o change, the effective capacitance is less because R n
increases the impedance of the C n.1 branch. As Figure 22 shows,
V o tends to dip when C n is too small, and this effect reduces the
V o ring-back. This effect is more pronounced when C n.1 is much
larger than C n.2 . It is also more pronounced when R n is bigger.
However, the presence of R n increases the ripple of the V n signal
if C n.2 is too small. It is recommended to keep C n.2 greater than
2200pF. R n value usually is a few ohms. C n.1 , C n.2 and R n values
should be determined through tuning the load transient response
January 8, 2013
FN7801.1
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| ISL6267HRZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLR FOR AMD FUSION UP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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