参数资料
| 型号： | ISL6267HRZ |
| 厂商： | Intersil |
| 文件页数： | 27/33页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR MULTIPHASE 48TQFN |
| 标准包装： | 50 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.013 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 管件 |
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ISL6267
Load Line Slope
See Figure 15 for load-line implementation.
For inductor DCR sensing, substitution of Equation 28 into
Equation 2 gives the load-line slope expression in Equation 35:
of the sensed output voltage, and then feeds it to the
compensator. T1 is measured after the summing node, and T2 is
measured in the voltage loop before the summing node. The
spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s)
can actually be measured on an ISL6267 regulator.
V droop 2R droop R ntcnet DCR
I o R i R sum
LL = ------------------ = ---------------------- × ----------------------------------------- × ------------
N
N
R ntcnet + --------------
(EQ. 35)
Q1
L
V O
V droop 2R sen × R droop
N × R i
I o
For resistor sensing, substitution of Equation 32 into Equation 2
gives the load line slope expression in Equation 36:
(EQ. 36)
LL = ------------------ = -----------------------------------------
V IN
GATE
DRIVER
Q2
C OUT
LOAD LINE SLOPE
i O
R droop = ---------------- × LL
I o
I droop
Ω
Substitution of Equation 29 and rewriting Equation 35, or
substitution of Equation 33 and rewriting Equation 36, gives the
same result as in Equation 37:
(EQ. 37)
MOD.
COMP
CHANNEL B
EA
-
+
VID
20
+
+
ISOLATION
TRANSFORMER
One can use the full-load condition to calculate R droop . For
example, given I omax = 51A, I droopmax = 40.9μA and
LL = 1.9m Ω , Equation 37 gives R droop = 2.37k Ω .
LOOP GAIN =
CHANNEL A
CHANNEL A
NETWORK
ANALYZER
EXCITATION OUTPUT
CHANNEL B
It is recommended to start with the R droop value calculated by
Equation 37 and fine-tune it on the actual board to get accurate
load-line slope. One should record the output voltage readings at
no load and at full load for load-line slope calculation. Reading
the output voltage at lighter load instead of full load will increase
the measurement error.
Compensator
Figure 21 shows the desired load transient response waveforms.
Figure 27 shows the equivalent circuit of a voltage regulator (VR)
with the droop function. A VR is equivalent to a voltage source
FIGURE 28. LOOP GAIN T1(s) MEASUREMENT SET-UP
T1(s) is the total loop gain of the voltage loop and the droop loop.
It always has a higher crossover frequency than T2(s), therefore
has a higher impact on system stability.
T2(s) is the voltage loop gain with closed droop loop, thus having
a higher impact on output voltage response.
Design the compensator to get stable T1(s) and T2(s) with sufficient
phase margin and an output impedance equal to or smaller than
the load-line slope.
(= VID) and output impedance Z out (s). If Z out (s) is equal to the
load-line slope LL, i.e., a constant output impedance, then in the
entire frequency range, V o will have a square response when I o
has a square change.
Q1
L
V O
Z out (s) = LL
i
o
V IN
GATE
DRIVER
Q2
C O
I O
LOAD LINE SLOPE
VID
VR
LOAD
V
o
MOD.
EA
-
+
+
20
Ω
COMP
+
VID
ISOLATION
TRANSFORMER
CHANNEL B
FIGURE 27. VOLTAGE REGULATOR EQUIVALENT CIRCUIT
LOOP GAIN =
CHANNEL A
Intersil provides a Microsoft Excel-based spreadsheet to help
design the compensator and the current sensing network so that
VR achieves constant output impedance as a stable system.
CHANNEL A
NETWORK
ANALYZER
EXCITATION OUTPUT
CHANNEL B
A VR with active droop function is a dual-loop system consisting of
a voltage loop and a droop loop, which is a current loop. However,
neither loop alone is sufficient to describe the entire system. The
spreadsheet shows two loop gain transfer functions, T1(s) and
T2(s), that describe the entire system. Figure 28 conceptually
shows T1(s) measurement set-up, and Figure 29 conceptually
shows T2(s) measurement set-up. The VR senses the inductor
current, multiplies it by a gain of the load-line slope, adds it on top
27
FIGURE 29. LOOP GAIN T2(s) MEASUREMENT SET-UP
Current Balancing
Refer to Figures 16 through 20 for information on current
balancing. The ISL6267 achieves current balancing through
matching the ISEN pin voltages. R isen and C isen form filters to
remove the switching ripple of the phase node voltages. It is
recommended to use a rather long R isen C isen time constant such
January 8, 2013
FN7801.1
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| ISL6267HRZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLR FOR AMD FUSION UP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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