参数资料
| 型号： | ISL6267HRZ |
| 厂商： | Intersil |
| 文件页数： | 20/33页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR MULTIPHASE 48TQFN |
| 标准包装： | 50 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.013 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页当前第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页
ISL6267
amplifier regulates the inverting and non-inverting input voltages
to be equal as shown in Equation 3:
Rdroop
Vdroop
FB
+
-
VCC SENSE
VR LOCAL VO
VCC SENSE + V
droop
= V DAC + VSS SENSE
(EQ. 3)
COMP
+
E/A
-
INTERNAL TO IC
Idroop
Σ VDAC
+
DAC
X1
+
-
“CATCH” RESISTOR
VIDs
VID<0:7>
RTN
VSS SENSE
VSS
Rewriting Equation 3 and substituting Equation 2 gives
Equation 4 is the exact equation required for load-line
implementation.
VCC SENSE – VSS SENSE = V DAC – R droop × I droop
(EQ. 4)
“CATCH” RESISTOR
FIGURE 15. DIFFERENTIAL SENSING AND LOAD LINE
IMPLEMENTATION
As the load current increases from zero, the output voltage
droops from the VID table value by an amount proportional to the
load current, to achieve the load line. The ISL6267 can sense the
inductor current through the intrinsic DC Resistance (DCR) of the
inductors, as shown in Figures 15 and 16, or through resistors in
The VCC SENSE and VSS SENSE signals come from the processor die.
The feedback is an open circuit in the absence of the processor. As
Figure 15 shows, it is recommended to add a “catch” resistor to feed
the VR local output voltage back to the compensator, and to add
another “catch” resistor to connect the VR local output ground to the
RTN pin. These resistors, typically 10 Ω ~100 Ω , provide voltage
feedback if the system is powered up without a processor installed.
Phase Current Balancing
series with the inductors as shown in Figure 17. In both methods,
capacitor C n voltage represents the inductor total currents. A
droop amplifier converts C n voltage into an internal current
source with the gain set by resistor R i . The current source is used
for load line implementation, current monitoring and overcurrent
protection.
Figure 15 shows the load-line implementation. The ISL6267
ISEN3
INTERNAL
INTERNAL
TO IC
ISEN2
PHASE3
R isen
C isen
PHASE2
R isen
L3
L2
I L3
I L2
R dcr3
R dcr2
R pcb3
R pcb2
V O
drives a current source (I droop ) out of the FB pin, as described by
Equation 1.
C isen
PHASE1
L1
R dcr1
R pcb1
R i
2xV Cn
I droop = ----------------
(EQ. 1)
ISEN1
R isen
C isen
I L1
When using inductor DCR current sensing, a single NTC element
is used to compensate the positive temperature coefficient of the
copper winding, thus sustaining the load-line accuracy with
reduced cost.
I droop flows through resistor R droop and creates a voltage drop as
shown in Equation 2.
FIGURE 16. CURRENT BALANCING CIRCUIT
The ISL6267 monitors individual phase average current by
monitoring the ISEN1, ISEN2, and ISEN3 voltages. Figure 16
shows the current balancing circuit recommended for the
ISL6267. Each phase node voltage is averaged by a low-pass
filter consisting of R isen and C isen , and is presented to the
corresponding ISEN pin. R isen should be routed to the inductor
phase-node pad in order to eliminate the effect of phase node
V droop = R droop × I droop
(EQ. 2)
parasitic PCB DCR. Equations 5 through 7 give the ISEN pin
voltages:
V droop is the droop voltage required to implement load line.
Changing R droop or scaling I droop can change the load line slope.
Since I droop sets the overcurrent protection level, it is
recommended to first scale I droop based on OCP requirement,
then select an appropriate R droop value to obtain the desired
load line slope.
Differential Sensing
V ISEN1 = ( R dcr1 + R pcb1 ) × I L1
V ISEN2 = ( R dcr2 + R pcb2 ) × I L2
V ISEN3 = ( R dcr3 + R pcb3 ) × I L3
(EQ. 5)
(EQ. 6)
(EQ. 7)
Figure 15 shows the differential voltage sensing scheme.
VCC SENSE and VSS SENSE are the remote voltage sensing signals
from the processor die. A unity gain differential amplifier senses
the VSS SENSE voltage and adds it to the DAC output. The error
20
where R dcr1 , R dcr2 and R dcr3 are inductor DCR; R pcb1 , R pcb2
and R pcb3 are parasitic PCB DCR between the inductor output
side pad and the output voltage rail; and I L1 , I L2 and I L3 are
inductor average currents.
January 8, 2013
FN7801.1
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