参数资料
| 型号： | ISL6267HRZ |
| 厂商： | Intersil |
| 文件页数： | 8/33页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR MULTIPHASE 48TQFN |
| 标准包装： | 50 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.013 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页
ISL6267
Pin Descriptions (Continued)
PIN NUMBER
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
SYMBOL
ISEN3/FB2
ISEN2
ISEN1
VSEN
RTN
ISUMN
ISUMP
VDD
VIN
PROG1
BOOT1
UG1
PH1
LG1
PWM3
VCCP
LG2
PH2
UG2
BOOT2
PWM2_NB
LG1_NB
PH1_NB
UG1_NB
8
DESCRIPTION
When the Core VR of ISL6267 is configured in 3-phase mode, this pin is ISEN3. ISEN3 is the individual
current sensing for Channel 3. When the Core VR of ISL6267 is configured in 2-phase mode, this pin is
FB2. There is a switch between the FB2 pin and the FB pin. The switch is on in 2-phase mode and is off
in 1-phase mode. The components connecting to FB2 are used to adjust the compensation in 1-phase
mode to achieve optimum performance.
Individual current sensing for Channel 2 of the Core VR. When ISEN2 is pulled to 5V VDD, the controller
disables Channel 2, and the Core VR runs in single-phase mode.
Individual current sensing for Channel 1 of the Core output.
Output voltage sense pin for the Core controller. Connect to the +sense pin of the microprocessor die.
Output voltage sense return pin for the Core controller. Connect to the -sense pin of the microprocessor
die.
Inverting input of the transconductance amplifier for current monitor and load line of Core output.
Non-inverting input of the transconductance amplifier for current monitor and load line of Core output.
5V bias power.
Battery supply voltage, used for feed-forward.
Program pin for setting output voltage offset for Core VR.
Connect an MLCC capacitor across the BOOT1 and the phase (PH1) pin. The boot capacitor is charged
through an internal boot diode connected from the VCCP pin to the BOOT1 pin, each time the PH1 pin
drops below VCCP minus the voltage dropped across the internal boot diode.
Output of the Phase 1 high-side MOSFET gate driver of the Core VR. Connect the UG1 pin to the gate of
the Phase 1 high-side MOSFET.
Current return path for the Phase 1 high-side MOSFET gate driver of VR1. Connect the PH1 pin to the node
consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of
Phase 1.
Output of the Phase 1 low-side MOSFET gate driver of the Core VR. Connect the LG1 pin to the gate of the
Phase 1 low-side MOSFET.
PWM output for Channel 3 of the Core VR. When PWM3 is pulled to 5V VDD, the controller disables Phase
3 and runs in 2-phase mode.
Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at least 1μF
of capacitance to GND. A high quality, X7R dielectric MLCC capacitor is recommended.
Output of the Phase 2 low-side MOSFET gate driver of VR1. Connect the LG2 pin to the gate of the
Phase 2 low-side MOSFET.
Current return path for the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the PH2 pin to
the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor
of Phase 2.
Output of the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the UG2 pin to the gate of
the Phase 2 high-side MOSFET.
Connect an MLCC capacitor across the BOOT2 and PH2 pins. The boot capacitor is charged through an
internal boot diode connected from the VCCP pin to the BOOT2 pin, each time the PH2 pin drops below
VCCP minus the voltage dropped across the internal boot diode.
PWM output for Channel 2 of the Northbridge VR.
Output of the low-side MOSFET gate driver of the Northbridge VR. Connect the LG1_NB pin to the gate of
the low-side MOSFET of VR2.
Current return path for the high-side MOSFET gate driver of the Northbridge VR. Connect the PH1_NB pin
to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of the Northbridge VR.
Output of the high-side MOSFET gate driver of the Northbridge VR. Connect the UG1_NB pin to the gate
of the high-side MOSFET.
January 8, 2013
FN7801.1
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