参数资料
| 型号： | ISL6267HRZ |
| 厂商： | Intersil |
| 文件页数： | 16/33页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR MULTIPHASE 48TQFN |
| 标准包装： | 50 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.013 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 管件 |
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ISL6267
Hysteresis between the rising and the falling thresholds assure
VDD
the ISL6267 does not inadvertently turn off unless the bias
ENABLE
SLEW RATE
1.875mV/μs
MetalVID VID COMMAND
800μs VOLTAGE
voltage drops substantially (see “Electrical Specifications” on
page 11).
Serial VID Interface
DAC
PGOOD
PWROK
VIN
FIGURE 12. TYPICAL SOFT-START WAVEFORMS
Power-On Reset
Before the controller has sufficient bias to guarantee proper
operation, the ISL6267 requires both a +5V input supply tied to
V CC and PV CC , as well as a battery or other input supply tied to
V IN , to exceed their respective rising power-on reset (POR)
thresholds. Once these thresholds are reached or exceeded, the
ISL6267 has enough bias to begin checking SVI inputs.
The on-board Serial VID Interface (SVI) circuitry allows the
processor to directly control the Core and Northbridge voltage
reference levels within the ISL6267. The SVC and SVD states are
decoded according to the PWROK inputs as described in the
following sections. The ISL6267 uses a digital-to-analog
converter (DAC) to generate a reference voltage based on the
decoded SVI value. See Figure 13 for a simple SVI interface
timing diagram.
Pre-PWROK Metal VID
Typical motherboard start-up begins with the controller decoding
the SVC and SVD inputs to determine the pre-PWROK Metal VID
setting (see Table 1). Once the ENABLE input exceeds the rising
threshold, the ISL6267 decodes and locks the decoded value in
an on-board hold register.
1
2
3
4
5
6
7
8
9
10
11
12
VCC
SVC
SVD
ENABLE
PWROK
METAL_VID
V_SVI
METAL_VID
V_SVI
V CORE / V NB
PGOOD
Interval 1 to 2: ISL6267 waits to POR.
Interval 2 to 3: SVC and SVD are externally set to pre-Metal VID code.
Interval 3 to 4: ENABLE locks pre-Metal VID code. All outputs soft-start to this level.
Interval 4 to 5: PGOOD signal goes HIGH, indicating proper operation.
Interval 5 to 6: CPU detects PGOOD high, and drives PWROK high, to allow ISL6267 to prepare for SVI commands.
Interval 6 to 7: SVC and SVD data lines communicate change in VID code.
Interval 7 to 8: ISL6267 responds to VID-ON-THE-FLY code change.
Interval 8 to 9: PWROK is driven low, and ISL6267 returns all outputs to pre-PWROK Metal VID level.
Interval 9 to 10: PWROK driven high once again by CPU, and ISL6267 prepares for SVI commands.
Interval 10 to 11: SVC and SVD data lines communicate new VID code.
Interval 11 to 12: ISL6267 drives outputs to new VID code level.
Post 12: Enable falls, all internal drivers are tri-stated, and PGOOD is driven low.
FIGURE 13. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP
16
January 8, 2013
FN7801.1
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