参数资料
| 型号： | ISL6267HRZ |
| 厂商： | Intersil |
| 文件页数： | 19/33页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR MULTIPHASE 48TQFN |
| 标准包装： | 50 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.013 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页
ISL6267
See Table 3
SVID
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SVC
SVD
SLAVE ADDRESS PHASE
FIGURE 14. SEND BYTE EXAMPLE
DATA PHASE
SVI Bus Protocol
The AMD processor bus protocol is compliant with SMBus send
byte protocol for VID transactions (see Figure 14). During a send
byte transaction, the processor sends the start sequence
followed by the slave address of the VR for which the VID
command applies. The address byte must be configured
according to Table 3. The processor then sends the write bit. After
VR Offset Programming
A positive or negative offset is programmed for the Core VR using
a resistor to ground from the PROG1 pin and the Northbridge in a
similar manner from the PROG2 pin. Table 5 provides the resistor
value to select the desired output voltage offset
TABLE 5. PROGx PIN RESISTOR VALUE
the write bit, if the ISL6267 receives a valid address byte, it
sends the acknowledge bit. The processor then sends the PSI-L
bit and VID bits during the data phase. The Serial VID 8-bit data
field encoding is outlined in Table 4. If the ISL6267 receives a
valid 8-bit code during the data phase, it sends the acknowledge
bit. Finally, the processor sends the stop sequence. After the
ISL6267 has detected the stop, it can then proceed with the
VID-on-the-fly transition.
TABLE 3. SVI SEND BYTE ADDRESS DESCRIPTION
BITS DESCRIPTION
6:4 Always 110b
3 Reserved by AMD for future use
2 VDD1; if set, then the following data byte contains the VID for
VDD1 [Note: The ISL6267 does not support VDD1]
RESISTOR
VALUE
[ Ω ]
0
590
1100
1690
2260
3160
4320
5620
6650
PROG1
V CORE OFFSET
[mV]
50
43.75
37.50
31.25
25.00
18.75
12.50
6.25
0.00
PROG1
VNBOFFSET
[mV]
50
43.75
37.50
31.25
25.00
18.75
12.50
6.25
0.00
1
0
BITS
7
VDD0; if set, then the following data byte contains the VID for
VID0
VDDNB; if set then the following data byte contains the VID for
VIDNB
TABLE 4. SERIAL VID 8-BIT DATA FIELD ENCODING
DESCRIPTION
PSI_L:
7870
9530
11500
14000
16500
18700
OPEN
-6.25
-12.50
-18.75
-25.00
-31.25
-37.50
-43.75
-6.25
-12.50
-18.75
-25.00
-31.25
-37.50
-43.75
=0 means the processor is at an optimal load for the regulators
to enter power-saving mode
=1 means the processor is not at an optimal load for the
regulators to enter power-saving mode
6:0 SVID[6:0] as defined in Table 2.
Operation
After the start-up sequence, the ISL6267 begins regulating the
Core and Northbridge output voltages to the pre-PWROK metal
VID programmed. The controller monitors SVI commands to
determine when to enter power-saving mode, implement
dynamic VID changes, and shut down individual outputs.
19
Voltage Regulation and Load Line
Implementation
After the start sequence, the ISL6267 regulates the output voltage
to the value set by the VID information, per Table 2. The ISL6267
controls the no-load output voltage to an accuracy of ±0.5% over
the range of 0.75V to 1.55V. A differential amplifier allows
voltage sensing for precise voltage regulation at the
microprocessor die.
January 8, 2013
FN7801.1
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