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L64005 MPEG-2 Audio/Video Decoder Technical Manual
2-57
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
2.9.14
Group 7
Main/Serration
Lines
The Main Lines[7:3] eld of Register 22, the Main/Serration Lines Reg-
ister, contains the least signicant byte of the number of scan lines in the
active portion of the image per eld, divided by eight. There must be an
exact multiple of eight scan lines in the active image area. The MSB of
this eld is stored in the ML[8] bit in Register 24. Main Lines [2:0] (not
shown) are hardwired to zero. The Serration Lines eld of Register 22
also contains the number of half scan lines of serration.
2.9.15
Group 7
Scan Half Lines
Register 23, the Scan Half Lines Register, contains the number of half
scan lines from post-equalization in one eld to pre-equalization in the
next eld. The sum of pre-equalization, post-equalization, serration and
scan half lines is equal to the total number of halines in a eld. The
MSB of the Scan Half Lines Register is located in Register 25. The LSB
of the Scan Half Lines Register is hardwired to guarantee an odd number
of half lines in a eld.
Figure 2.10
Scan Half Lines
Register
2.9.16
Group 7
Main Reads Per
Line
Register 24, the Main Reads Per Line Register, contains the number of
reads required to construct a scan line for display. This is a function of
the displayed picture width and is equal to one-eighth of the width. Refer
75
4
0
Serration Lines
Main Lines[7:3]
Register 22
98
1
0
Register 25, Bit 7 (MSB)
Register 23, Bits [7:0](LSB)
0
70
Scan Half Lines[8:1]
Register 23