
L64005 MPEG-2 Audio/Video Decoder Technical Manual
2-39
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
2.8.26
Group 6
Video Channel
Buffer End
Address
The Video Channel Buffer End Address Registers supply the end
address of the Video Channel buffer. For a detailed description on the
use of this eld refer to
Chapter 8. The address value stored in Registers
42 and 43 is in 256-byte (thirty-two 8-byte DRAM words) resolution.
These registers provide the upper 13 bits of address. The implied lower
address bits (not shown, but required to make a full 8-byte DRAM word
address) are set internally to 111112. These registers are read/write.
2.8.27
Group 6
Audio Channel
Buffer Start
Address
The Audio Channel Buffer Start Address Registers supply the start
address of the Audio Channel buffer. For a detailed description on the
use of this eld refer to
Chapter 8. The address value stored in Registers
44 and 45 is in 256-byte (thirty-two 8-byte DRAM words) resolution.
These registers provide the upper 13 bits of the audio channel buffer
start address. The implied lower address bits (not shown, but required to
make a full 8-byte DRAM word address) are set internally to 000002.
These registers are read/write.
70
Video Channel Buffer Start Address (LSB)
Register 40
74
0
RESERVED
Video Channel Buffer Start Address (MSB)
Register 41
70
Video Channel Buffer End Address (LSB)
Register 42
75
4
0
RESERVED
Video Channel Buffer End Address (MSB)
Register 43