
2-38
Registers
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
2.8.24
Group 6
Audio PES
Buffer End
Address
The Audio PES Buffer End Address Registers supply the end address of
the Audio PES Data buffer. For a detailed description on the use of these
registers refer to
Chapter 8. The address value stored in Registers 38
and 39 is in 256-byte (thirty-two 8-byte DRAM words) resolution. These
registers provide the upper 13 bits of the audio PES buffer end address.
The implied lower address bits (not shown, but required to make a full 8-
byte DRAM word address) are set internally to 111112. These registers
are read/write.
2.8.25
Group 6
Video Channel
Buffer Start
Address
The Video Channel Buffer Start Address Registers supply the start
address of the Video Channel buffer. For a detailed description on the
use of this eld refer to
Chapter 8. The address value stored in Registers
40 and 41 is in 256-byte (thirty-two 8-byte DRAM words) resolution.
These registers provide the upper 13 bits of the video channel buffer
start address. The implied lower address bits (not shown, but required to
make a full 8-byte DRAM word address) are set internally to
000002.These registers are read/write.
70
Audio PES Buffer Start Address (LSB)
Register 36
75
4
0
Reserved
Audio PES Buffer Start Address (MSB)
Register 37
70
Audio PES Buffer End Address (LSB)
Register 38
75
4
0
RESERVED
Audio PES Buffer End Address (MSB)
Register 39