
L64005 MPEG-2 Audio/Video Decoder Technical Manual
A-3
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
Figure A.17
5V Interface
Congurations
For each conguration, a special purpose 5-V compatible I/O buffer is
available in the technology used for L64005, which accepts signal voltage
levels exceeding the 3.3-V on-chip power supply during normal system
operation.
5-V compatible buffers are designed to interface to 5-V ICs
without being true 5-V I/Os—they do not need a 5-V power supply on-
chip.
A.2.5
5V-Compatible
Input Buffers
5-V compatible input buffers on the L64005 are designed to:
Accept valid TTL or 5-V CMOS input levels at the device pad and
guarantee proper switching
Limit voltage stress on any internal transistor to less than the maxi-
mum 3.63 V allowed across any two device terminals
Provide adequate AC performance
Exhibit acceptable levels of input leakage current in the input stage
Accept 5-V DC signals with minimal input leakage current into the
ESD protection circuitry
Withstand transient voltages similar to the maximum transient volt-
ages accepted by 5-V ICs (VIN = 6.5V)
A.2.5.1 DC Characteristics
Table A.12 shows the DC characteristics . All limits are specied over
commercial conditions. Note that absolute maximum limits for voltage
undershoot and overshoot are -1.0 V and +6.5 V.
5 V
5 V IC
L64005
3.3 V
Bidirectional
Buffer
Open
Drain
Output
5 V
R
5 V
5 V IC
3-State
Buffer
Input
Output