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L64005 MPEG-2 Audio/Video Decoder Technical Manual
2-61
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
BAL
Blank Active Low
4, R/W
When set, BAL selects the blank output to be active
LOW. When clear, BAL selects the blank output to be
active HIGH.
SAL
Sync Active Low
3, R/W
When set, SAL sets the syncs to be active LOW. When
clear, SAL selects the syncs to be active HIGH.
CMS
Composite Sync Mode
2, R/W
When set, CMS causes the decoder to output composite
sync on the HS pin. When clear, CMS causes the
decoder to output separate HS and VS signals.
DMM
Display Master Mode
1, R/W
When set, DMM causes the display controller on the
L64005 to drive the VS and HS pins. When DMM is clear,
these pins are inputs, and the L64005 locks to an exter-
nal sync source.
CCIR
CCIR 601 Mode
0, R/W
When set, CCIR causes the pixel output port to transmit
CCIR601 SAV and EAV codes with the pixels.
2.9.22
Group 7
Channel Buffer
Read Address
Registers 32 through 39 contain the read and write pointers for the four
channel buffers. These channel buffer read and write pointers indicate
the fullness of the channel buffer. They are expressed in 8-byte resolu-
tion. Note that the channel buffer is implemented as a circular FIFO. The
four MSBs of the address indicate the number of times that the pointer
has reached the top of the FIFO and rolled over. The external controller
may need to perform some offsetting if physical memory space wraps
around. Note also that there is no read pointer for the PES FIFOs. The
host handles the read and needs to keep track of the location of the write
pointer to avoid overow or underow of the PES FIFOs. These registers
share a single NSB and MSB register for the next signicant and most
signicant addresses. Register 38 contains the NSB for Registers 32
through 37, and Register 39 contains the MSB for Registers 32 through
37. The NSB and MSB are loaded when there is a read to a LSB regis-
ter. The NSB and MSB contain the high order bits of the most recently
read LSB register. These registers are read only.
Register 32 contains the Video System Write Address
Register 33 contains the Audio System Write Address