
L64005 MPEG-2 Audio/Video Decoder Technical Manual
5-1
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
Chapter 5
External Memory
Interface
This chapter describes the L64005’s frame memory interface. This chap-
ter contains the following sections:
5.1
Overview
The L64005’s built-in controllers allow frame memories to decode and
display an MPEG bit stream. The L64005 can access memory through
a 64-bit data bus in regular DRAM mode and through a 16-bit data bus
in synchronous DRAM mode.The interface is optimized to operate at res-
olutions up to 720 x 576 pixels. Lower resolution images may require less
memory, but they are still accessed over the same interface.
5.2
Memory
Architecture
An internal unied 64-bit memory interface supports accesses to frame
stores, the channel buffer, and the display processor. The L64005 allo-
cates a slice of the available memory bandwidth to each of these func-
tions in proportion to its needs. In the regular DRAM interface Mode most
accesses to memory are performed in fast page mode.
Normally three frames of memory are needed for frame stores in an
MPEG decoder, depending on the constraints in the bit stream and the
mode of the display. The remaining memory is divided between the audio
and video channel buffers, the OSD, and the vertical blanking interval
(VBI) data. VBI data represents pixels in the vertical blanking interval.
The total amount of memory in bytes is determined by the picture size