
2-36
Registers
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
Figure 2.7
LAF and ODFF Bit
Fields
BTF
Bottom/Top Field Indicator
1, R
The L64005 sets BTF at the rst horizontal sync after a
vertical sync when Bottom Field data is being displayed.
The L64005 clears BTF at the rst horizontal sync after
a vertical sync when Top Field data is being displayed.
This bit is initially synchronized to EOF (top=odd) and
remains synchronized until such time that a eld inver-
sion occurs.
EOF
Even/Odd Field Indicator
0, R
The L64005 sets EOF at the rst horizontal sync after a
vertical sync during an even eld. The L64005 clears
EOF at the rst horizontal sync after a vertical sync dur-
ing an odd eld. The rst picture output by the display
controller will begin on an odd eld.
2.8.21
Group 6
Video PES
Buffer Start
Address
The Video PES Buffer Start Address Registers supply the start address
of the Video PES data buffer. For a detailed description on the use of
this eld refer to
Chapter 8. The address value stored in Registers 32
and 33 is in 256-byte (thirty-two 8-byte DRAM words) resolution. This
register provides the upper 13 bits of the video PES buffer start address.
The implied lower address bits (not shown, but required to make a full 8-
byte DRAM word address) are set internally to 000002. These registers
are read/write.
3:2 Pulldown
New Field
Last Active Field
Odd Field First
OEOE
OEOE O
MD96.230
(3 eld)
(2 eld)