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参数资料
| 型号： | M295V002T-120XP1TR |
| 厂商： | 意法半导体 |
| 英文描述： | 2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
| 中文描述： | 2兆位的256Kb × 8，启动座单电源闪存 |
| 文件页数： | 10/29页 |
| 文件大小： | 196K |
| 代理商： | M295V002T-120XP1TR |
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See Figure 11 for the Data Polling flowchart and
Figure10 fortheData Pollingwaveforms.DQ7 will
also flag the Erase Suspend mode by switching
from ’0’ to ’1’ at the start of the Erase Suspend. In
order to monitorDQ7 in the EraseSuspend mode
an address within a block being erased must be
provided.For aRead Operationin EraseSuspend
mode, DQ7 will output ’1’ if the read is attempted
onablockbeingerasedandthedatavalueonother
blocks. During Program operation in Erase Sus-
pend Mode, DQ7 will have the same behaviouras
in the normal program execution outside of the
suspendmode.
Toggle Bit (DQ6).
WhenProgrammingor Erasing
operationsarein progress,successiveattemptsto
readDQ6willoutputcomplementarydata.DQ6will
toggle following toggling of either G, or E when G
is low. The operationis completedwhen two suc-
cessivereadsyieldthesameoutputdata.Thenext
readwilloutputthe bitlastprogrammedora’1’after
erasing. The toggle bit DQ6 is valid only during
P/E.C. operations, that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the blocks selected for erasure are pro-
tected, DQ6 will toggle for about 100
μ
s and then
returnback toRead. DQ6will besetto’1’if aRead
operationisattemptedon anEraseSuspendblock.
When erase is suspendedDQ6 will toggle during
programming operationsin a blockdifferentto the
block in EraseSuspend.Either E or G togglingwill
causeDQ6 to toggle. See Figure 12 for ToggleBit
flowchartand Figure 13 for ToggleBit waveforms.
Toggle Bit (DQ2).
This toggle bit, together with
DQ6, can be used to determine the device status
duringthe Eraseoperations.It can alsobe usedto
identify the block being erased. During Erase or
Erase Suspend a read from a block being erased
will cause DQ2 to toggle. A read from a block not
being erased will set DQ2 to ’1’ during erase and
to DQ2 during Erase Suspend.During Chip Erase
a read operation will cause DQ2 to toggle as all
blocks are being erased. DQ2 will be set to ’1’
duringprogramoperationand when erase is com-
plete. After erase completion and if the error bit
DQ5 is set to ’1’, DQ2 will toggle if the faulty block
is addressed.
Error Bit (DQ5).
This bit is set to ’1’ by the P/E.C.
when there is a failure of programming, block
erase, or chip erase that resultsin invalid data in
thememoryblock.In caseof anerrorinblockerase
or program,the block inwhichtheerror occuredor
to which the programmed data belongs, must be
discarded. The DQ5 failure condition will also ap-
pearifa usertriesto programa’1’toa locationthat
is previouslyprogrammedto ’0’. OtherBlocksmay
stillbe used.TheerrorbitresetsafteraRead/Reset
(RD)instruction. In caseof successof Program or
Erase, the error bit will be set to ’0’.
EraseTimer Bit (DQ3).
Thisbit is setto ’0’ by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
periodis finished,after50
μ
s to120
μ
s,DQ3returns
to ’1’.
Coded Cycles
The two Coded cyclesunlockthe CommandInter-
face.They are followedby an input commandor a
confirmationcommand.The Codedcycles consist
of writing the dataAAh at address555h duringthe
first cycle. During the second cycle the Coded
cycles consist of writing the data 55h at address
AAAh.Theaddresslines A0 to A11arevalid,other
address lines are ’don’t care’. The Coded cycles
happenonfirstandsecondcyclesof thecommand
writeor on thefourth and fifthcycles.
Instructions
SeeTable 8.
Read/Reset (RD) Instruction.
The Read/Reset
instruction consists of one write cycle giving the
commandF0h.It canbe optionallyprecededbythe
twoCodedcycles.Subsequentreadoperationswill
read the memory array addressed and output the
data read. A wait stateof 10
μ
s is necessaryafter
Read/Reset prior to any valid read if the memory
was in an Erase mode when the RD instructionis
given.
Mode
DQ7
DQ6
DQ2
Program
DQ7
Toggle
1
Erase
0
Toggle
Note 1
Erase Suspend Read
(in EraseSuspend
block)
1
1
Toggle
Erase Suspend Read
(outside Erase Suspend
block)
DQ7
DQ6
DQ2
Erase Suspend Program
DQ7
Toggle
N/A
Note:
1. Toggle if the address is within a block being erased.
’1’ if the address is within a block not being erased.
Table10. Pollingand Toggle Bits
10/29
M29F002T, M29F002NT, M29F002B
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相关代理商/技术参数 |
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|---|---|
| M295V002T-120XP6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
| M295V002T-70K1TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
| M295V002T-70K6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
| M295V002T-70N1TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
| M295V002T-70N6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
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