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参数资料
型号： M295V002T-120XP1TR
厂商： 意法半导体
英文描述： 2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory
中文描述： 2兆位的256Kb × 8，启动座单电源闪存
文件页数： 5/29页
文件大小： 196K
代理商： M295V002T-120XP1TR
Instructions
Seven instructions are defined to perform Read
Array,AutoSelect(to readtheElectronicSignature
or BlockProtectionStatus),Program,BlockErase,
Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handles all tim-
ing and verification of the Program and Erase
operations.The StatusRegisterData Polling, Tog-
gle, Error bits may be read at any time, during
programming or erase, to monitorthe progressof
the operation.
Instructionsare composedof upto six cycles. The
first two cycles input a Coded sequence to the
CommandInterfacewhich iscommontoall instruc-
tions (see Table 8). The third cycle inputs the
instruction set-up command. Subsequent cycles
outputtheaddresseddata,ElectronicSignatureor
Block Protection Status for Read operations. In
orderto giveadditionaldataprotection,the instruc-
tionsfor Programand Blockor Chip Erase require
furthercommandinputs.ForaPrograminstruction,
the fourth command cycle inputs the addressand
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
further Codedsequence before the Erase confirm
commandon thesixth cycle.Erasure of a memory
blockmaybesuspended,inorderto readdatafrom
anotherblock or to programdata in anotherblock,
and then resumed.
When power is first applied or if V
CC
falls below
V
LKO
, the command interface is reset to Read
Array.
SIGNAL DESCRIPTIONS
See Figure 1 and Table1.
Address Inputs (A0-A17)
. The addressinputsfor
thememoryarrayarelatchedduringa writeopera-
tion on the falling edge of Chip Enable E or Write
EnableW. WhenA9 is raisedto V
ID
, eithera Read
ElectronicSignatureManufacturerorDeviceCode,
BlockProtectionStatusora WriteBlockProtection
or BlockUnprotectionisenableddependingon the
combinationof levelson A0,A1, A6,A12and A15.
DataInput/Outputs(DQ0-DQ7).
Theinputis data
to be programmed in the memory array or a com-
mand to be written to the C.I. Both are latched on
the rising edge of Chip Enable E or Write Enable
W. The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
registerData Polling bit DQ7,the ToggleBits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
impedance when the chip is deselected or the
outputsare disabled and when RPNC is at a Low
level.
Chip Enable (E).
The Chip Enable input activates
the memory control logic, input buffers, decoders
andsenseamplifiers.EHighdeselectsthememory
andreducesthepowerconsumptiontothestandby
level. E can also be used to control writing to the
command register and to the memory array, while
Wremainsat alowlevel.TheChipEnablemustbe
forced to V
ID
duringthe Block Unprotectionopera-
tion.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read
operation. When G is High the outputs are High
impedance. G must be forced to V
ID
level during
BlockProtectionand Unprotectionoperations.
WriteEnable(W).
Thisinputcontrolswritingto the
CommandRegisterand Addressand Datalatches.
Reset/Block Temporary Unprotect/No Connect
Input (RPNC).
The RPNC (not available for the
M29F002NT) input provides hardware reset and
protected block(s) temporary unprotection func-
tions. In read or write mode, the RPNC pin can be
left open (Not Connected)or held at V
IH
. Reset of
thememory is acheived bypulling RPNC to V
IL
for
atleast 500ns.When thereset pulseis given,if the
memory is in Read or Standby modes, it will be
availablefornewoperationsin 50nsaftertherising
edge of RPNC. If the memory is in Erase, Erase
Suspend or Program modes the reset will take
10
μ
s.Ahardwareresetduringan Eraseor Program
operationwill corrupt the data being programmed
or the sector(s) beingerased.
Temporary block unprotectionis made by holding
RPNCat V
ID
. Inthisconditionpreviouslyprotected
blocks can be programmed or erased. The transi-
tion of RPNC from V
IH
to V
ID
must slower than
500ns.When RPNC is returnedfrom V
ID
to V
IH
all
blocks temporarily unprotected will be again pro-
tected.
V
CC
Supply Voltage.
The power supply for all
operations(Read, Program and Erase).
V
SS
Ground.
V
SS
is the reference for all voltage
measurements.
DEVICEOPERATIONS
SeeTables 4, 5 and6.
Read.
Read operations are used to output the
contentsof the Memory Array, the ElectronicSig-
nature,the StatusRegister or the BlockProtection
Status. Both Chip Enable E and Output Enable G
must be low in order to read the output of the
memory.
5/29
M29F002T, M29F002NT, M29F002B
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