Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI(2)
Input Leakage Current
0V
≤
V
IN
≤
V
CC
±
1
μ
A
I
LO
Output Leakage Current
0V
≤
V
OUT
≤
V
CC
±
1
μ
A
I
LR1
RPNC Leakage Current High
RPNC = V
CC
±
1
μ
A
I
LR2
RPNC Leakage Current Low
RPNC = V
SS
–0.2
–10
μ
A
I
CC1
Supply Current (Read) TTLByte
E = V
IL
, G = V
IH
, f = 6MHz
20
mA
I
CC2
Supply Current (Standby) TTL
E = V
IH
1
mA
I
CC3
Supply Current (Standby) CMOS
E = V
CC
±
0.2V
100
μ
A
I
CC4(1)
Supply Current (Program or Erase)
Byte program, Block or
Chip Erase in progress
20
mA
V
IL
Input Low Voltage
–0.5
0.8
V
V
IH
Input High Voltage
2
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 5.8mA
0.45
V
V
OH
Output High VoltageTTL
I
OH
= –2.5mA
2.4
V
Output High Voltage CMOS
I
OH
= –100
μ
A
V
CC
–0.4V
V
V
ID
A9, E, G, RPNC High Voltage
11.5
12.5
V
I
ID
A9, E, G, RPNC High Current
A9, E, G or RPNC = V
ID
100
μ
A
V
LKO
Supply Voltage(Erase and
Program lock-out)
3.2
4.2
V
Note:
1. Sampled only,not 100% tested.
2. Except RPNC.
Table13. DC Characteristics
(T
A
= 0 to 70
°
C or –40 to85
°
C; V
CC
= 5V
±
10%)
Block Erase (BE) Instruction
. This instruction
uses a minimum of six write cycles. The Erase
Set-upcommand80his writtento address555hon
third cycle after the two Coded cycles. The Block
EraseConfirmcommand30his similarlywrittenon
the sixth cycle after another two Coded cycles.
During the input of the second command an ad-
dress within the block to be erased is given and
latched into the memory. Additional block Erase
Confirm commands and block addresses can be
written subsequentlyto erase other blocksin par-
allel, without further Coded cycles. The erase will
start after the erase timeout period (see Erase
Timer Bit DQ3description).Thus,additionalErase
Confirm commandsfor otherblocks mustbe given
withinthisdelay. Theinputof anew EraseConfirm
commandwillrestartthetimeoutperiod.Thestatus
of the internal timer can be monitored throughthe
level of DQ3, if DQ3 is ’0’ the Block Erase Com-
mandhas been given and thetimeoutis running,if
DQ3 is ’1’, the timeout has expired and the P/E.C.
is erasing the Block(s). If the second command
givenis notaneraseconfirmor if theCodedcycles
arewrong,the instructionaborts,and thedeviceis
resetto ReadArray. It is not necessaryto program
the block with 00h as the P/E.C. will do this auto-
maticallybeforeto erasingto FFh.Readoperations
after the sixth rising edge of W or E output the
statusregisterstatus bits.
Duringtheexecutionof theerasebytheP/E.C.,the
memory accepts onlythe EraseSuspend ES and
Read/Reset RD instructions. Data Polling bit DQ7
returns ’0’ while the erasureis in progress and ’1’
when it has completed. The Toggle bit DQ2 and
DQ6 toggle during the erase operation. They stop
when erase is completed. After completion the
StatusRegisterbitDQ5returns’1’iftherehas been
an erase failure. In sucha situation,the Toggle bit
DQ2 can be used to determinewhich block is not
correctly erased. In the case of erase failure, a
Read/ResetRDinstructionis necessaryinorderto
reset the P/E.C.
12/29
M29F002T, M29F002NT, M29F002B