参数资料
型号: M295V002T-120XP1TR
厂商: 意法半导体
英文描述: 2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory
中文描述: 2兆位的256Kb × 8,启动座单电源闪存
文件页数: 8/29页
文件大小: 196K
代理商: M295V002T-120XP1TR
Mne.
Instr.
Cyc.
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc.
5th Cyc. 6th Cyc. 7th Cyc.
RD
(2,4)
Read/Reset
Memory Array
1+
Addr.
(3,7)
X
Read Memory Array until a new write cycle isinitiated.
Data
F0h
3+
Addr.
(3,7)
555h
AAAh
555h
Read Memory Array until a new write
cycle is initiated.
Data
AAh
55h
F0h
AS
(4)
Auto Select
3+
Addr.
(3,7)
555h
AAAh
555h
Read Electronic Signature orBlock
Protection Status until a new write cycle
is initiated. See Note 5 and 6.
Data
AAh
55h
90h
PG
Program
4
Addr.
(3,7)
555h
AAAh
555h
Program
Address
Read Data Polling or Toggle
Bit until Program completes.
Data
AAh
55h
A0h
Program
Data
BE
BlockErase
6
Addr.
(3,7)
555h
AAAh
555h
555h
AAAh
Block
Address
Additional
Block
(8)
Data
AAh
55h
80h
AAh
55h
30h
30h
CE
Chip Erase
6
Addr.
(3,7)
555h
AAAh
555h
555h
AAAh
555h
Note 9
Data
AAh
55h
80h
AAh
55h
10h
ES
(10)
Erase
Suspend
1
Addr.
(3,7)
X
Read until Toggle stops, then read all the data needed from
any Block(s) not being erased then Resume Erase.
Data
B0h
ER
Erase
Resume
1
Addr.
(3,7)
X
Read Data Polling or ToggleBits until Erase completes or
Erase is suspended another time
Data
30h
Notes:
1. Commands not interpreted in this table will default to read array mode.
2. Await of t
is necessary after a Read/Reset command if the memory was in an Erase or Program mode
before starting any new operation (see Table 14 and Figure 9).
3. X = Don’t Care.
4. The first cycles of the RD or AS instructions are followed by read operations.Any number of read cycles can occur after
the command cycles.
5. SignatureAddress bitsA0,A1 at V
IL
willoutput Manufacturer code (20h). Address bits A0at V
IH
andA1 at V
IL
will output
Device code.
6. Block Protection Address:A0 at V
, A1at V
and A13-A17within the Block will outputthe Block Protection status.
7. For Coded cycles address inputs A12-A17are don’t care.
8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last writeentry,
timeout status can be verified through DQ3 value (see EraseTimerBit DQ3 description).
When full commandis entered,read Data Polling or Togglebit until Erase is completed or suspended.
9. Read Data Polling, Toggle bits or RB until Erase completes.
10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
Table8. Instructions
(1)
Theinstructionsrequirefrom 1 to 6 cycles,the first
or first three of which are always write operations
usedtoinitiatetheinstruction.Theyarefollowedby
either further write cycles to confirm the first com-
mandor executethe commandimmediately.Com-
mand sequencing must be followed exactly. Any
invalid combination of commands will reset the
device to Read Array. The increased number of
cycles has been chosen to assure maximum data
security. Instructions are initialised by two initial
Coded cycles which unlock the Command Inter-
face.Inaddition,forErase,instructionconfirmation
is again precededby the two Coded cycles.
Status RegisterBits
P/E.C.statusis indicatedduring executionby Data
Polling on DQ7, detectionof Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mandexecutionwill automaticallyoutputthesefive
StatusRegisterbits.TheP/E.C. automaticallysets
bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits
(DQ0, DQ1 and DQ4) are reserved for future use
and should be masked. See Tables 9 and 10.
8/29
M29F002T, M29F002NT, M29F002B
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