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参数资料
| 型号： | M295V002T-120XP1TR |
| 厂商： | 意法半导体 |
| 英文描述： | 2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
| 中文描述： | 2兆位的256Kb × 8，启动座单电源闪存 |
| 文件页数： | 15/29页 |
| 文件大小： | 196K |
| 代理商： | M295V002T-120XP1TR |
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Symbol
Alt
Parameter
M29F002T / M29F002NT / M29F002B
Unit
-70
-90
-120
V
CC
= 5V
±
10%
V
CC
= 5V
±
10% V
CC
= 5V
±
10%
Standard
Interface
Standard
Interface
Standard
Interface
Min
Max
Min
Max
Min
Max
t
AVAV
t
WC
Address Validto Next Address
Valid
70
90
120
ns
t
ELWL
t
CS
Chip Enable Low to Write Enable
Low
0
0
0
ns
t
WLWH
t
WP
Write Enable Low to Write Enable
High
35
45
50
ns
t
DVWH
t
DS
Input Valid to Write Enable High
30
45
50
ns
t
WHDX
t
DH
Write Enable High to Input
Transition
0
0
0
ns
t
WHEH
t
CH
Write Enable High to Chip Enable
High
0
0
0
ns
t
WHWL
t
WPH
Write Enable High to Write Enable
Low
20
20
20
ns
t
AVWL
t
AS
Address Valid to Write Enable Low
5
5
5
ns
t
WLAX
t
AH
Write Enable Low to Address
Transition
45
45
50
ns
t
GHWL
Output EnableHigh to Write
Enable Low
0
0
0
ns
t
VCHEL
t
VCS
V
CC
High to Chip Enable Low
50
50
50
μ
s
t
WHGL
t
OEH
Write Enable High to Output
Enable Low
0
0
0
ns
t
PHPHH
(1,2)
t
VIDR
RPNC Rise Time to V
ID
500
500
500
ns
t
PLPX
t
RP
RPNC Pulse Width
500
500
500
ns
Notes:
1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotectionoperation.
Table15. WriteAC Characteristics,Write Enable Controlled
(T
A
= 0 to 70
°
C or –40 to85
°
C)
ChipErase(CE)Instruction.
Thisinstructionuses
six write cycles. The Erase Set-up command 80h
is written to address555h on the third cycle after
the two Coded cycles. The Chip Erase Confirm
command10h is similarly writtenon thesixthcycle
after another two Coded cycles. If the second
command given is not an erase confirm or if the
Codedcyclesarewrong,theinstructionabortsand
thedeviceisresettoReadArray.Itisnotnecessary
toprogramthearraywith00h firstastheP/E.C.will
automaticallydothisbeforeerasingittoFFh.Read
operations after the sixth rising edge of W or E
output the Status Register bits. During the execu-
tionof theerasebytheP/E.C.,DataPollingbit DQ7
returns ’0’, then ’1’ on completion. The Toggle bits
DQ2 and DQ6 toggle during erase operation and
stopwheneraseiscompleted.Aftercompletionthe
StatusRegisterbitDQ5returns’1’iftherehas been
an Erase Failure.
15/29
M29F002T, M29F002NT, M29F002B
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M295V002T-120XP6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
| M295V002T-70K1TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
| M295V002T-70K6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
| M295V002T-70N1TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
| M295V002T-70N6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
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