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参数资料
| 型号： | M295V002T-120XP1TR |
| 厂商： | 意法半导体 |
| 英文描述： | 2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
| 中文描述： | 2兆位的256Kb × 8，启动座单电源闪存 |
| 文件页数： | 9/29页 |
| 文件大小： | 196K |
| 代理商： | M295V002T-120XP1TR |
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DQ
Name
Logic Level
Definition
Note
7
Data
Polling
’1’
Erase Complete or erase
block in Erase Suspend
Indicates the P/E.C. status, check during
Program or Erase, and on completion
before checking bits DQ5 for Program or
Erase Success.
’0’
Erase On-going
DQ
Program Complete or data
of non erase block during
Erase Suspend
DQ
Program On-going
6
Toggle Bit
’-1-0-1-0-1-0-1-’
Erase or Program On-going
Successive reads outputcomplementary
data on DQ6 while Programming orErase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
DQ
Program Complete
’-1-1-1-1-1-1-1-’
Erase Complete or Erase
Suspend on currently
addressed block
5
Error Bit
’1’
Program or Erase Error
This bit is set to ’1’in the case of
Programming or Erase failure.
’0’
Program or Erase On-going
4
Reserved
3
Erase
Time Bit
’1’
Erase TimeoutPeriod Expired
P/E.C. Erase operation has started. Only
possible command entry isErase Suspend
(ES).
’0’
Erase TimeoutPeriod
On-going
An additional block to be erased in parallel
can be entered to the P/E.C.
2
Toggle Bit
’-1-0-1-0-1-0-1-’
Chip Erase, Erase or Erase
Suspend on the currently
addressed block.
Erase Error due to the
currently addressedblock
(when DQ5 = ’1’).
Indicates the erase status and allows to
identify the erased block
1
Program on-going,Erase
on-going on another block or
Erase Complete
DQ
Erase Suspend read on
non Erase Suspend block
1
Reserved
0
Reserved
Notes:
Logic level ’1’is High, ’0’ is Low.-0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
Table 9. StatusRegister Bits
Data Polling Bit (DQ7).
When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation,it outputsa ’0’.After com-
pletionof theoperation,DQ7will outputthe bitlast
programmed or a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourth W pulse for programmingor
after the sixth W pulse for erase. It must be per-
formedat theaddress beingprogrammedor at an
address within the block being erased. If all the
blocksselectedforerasureare protected,DQ7will
be setto ’0’forabout 100
μ
s, and thenreturnto the
previous addressedmemory datavalue.
9/29
M29F002T, M29F002NT, M29F002B
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相关代理商/技术参数 |
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| M295V002T-120XP6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
| M295V002T-70K1TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
| M295V002T-70K6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
| M295V002T-70N1TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
| M295V002T-70N6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory |
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