参数资料
型号: M30240M5-XXXFP
元件分类: 微控制器/微处理器
英文描述: 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80
封装: 0.80 MM PITCH, PLASTIC, QFP-80
文件页数: 73/139页
文件大小: 1453K
代理商: M30240M5-XXXFP
39
Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Specifications REV. G
Specifications in this manual are tentative and subject to change
Frequency Synthesizer Circuit
1.2.17.2 Multiplier
Clock fVCO is a multiplied up version of clock fPIN (See Figure 1.25). The relationship between fVCO
and the clock input to the multiplier (fPIN) from the prescaler is as follows:
fVCO = fPIN x 2(n+1) where n is the decimal equivalent of the value loaded in FSM.
Setting FSM to 255 disables the multiplier and fVCO = fPIN.
Note 1: n must be chosen such that fVCO equals 48 MHz.
Note 2: Minimum fPIN is 1 MHz.
Figure 1.25: Frequency Synthesizer Multiply Register (FSM)
1.2.17.3 Divider
Clock fSYN is a divided down version of clock fVCO (See Figure 1.26). The relationship between fSYN
and the clock input to the divider (fVCO) from the multiplier is as follows:
fSYN = fVCO / 2(m+1) where m is the decimal equivalent of the value loaded in FSD.
Setting FSD to 255 disables the divider and fSYN = fVCO.
Figure 1.26: Frequency Synthesizer Divide Register (FSD)
fPIN x 2(n+1) = fVCO
fPIN
FSM
fVCO
Dec(n)
Hex(n)
1 MHz
23
17
48.00 MHz
2 MHz
11
0B
48.00 MHz
4 MHz
5
05
48.00 MHz
6 MHz
3
03
48.00 MHz
12 MHz
1
01
48.00 MHz
MSB
7
LSB
0
Bit 6
Bit 1
Bit 0
Bit 2
Bit 5Bit 4Bit 3
Bit 7
Address: 03DD16
Access: R/W
Reset:
FF16
fVCO/2(m+1) = fSYN
fVCO
FSD
fSYN
Dec(m)
Hex(m)
48.00 MHz 1
01
12.00 MHz
48.00 MHz 127
7F
187.50 KHz
MSB
7
LSB
0
Bit 6
Bit 1
Bit 0
Address: 03DF16
Access: R/W
Reset:
FF16
Bit 2
Bit 5Bit 4Bit 3
Bit 7
相关PDF资料
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M30240M6-XXXXFP 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80
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