参数资料
型号: M66291GP
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封装: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件页数: 111/128页
文件大小: 928K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 81 of 122
3 M66291 OPERATIONS
3.1 Interrupt Function
There are 8 factors of interrupts in the M66291.
For details, refer to the “Interrupt Status Registers 0 to 3”.
The enable/disable of interrupt can be set by the Interrupt Enable Registers 0 to 3.
Each bit of the Interrupt Status Register is set to “1” according to the factor even if the Interrupt Enable
Registers 0 to 3 are set to interrupt inhibit mode.
The list of interrupts in M66291 is given in Table 3.1 and the diagrams related to the interrupt in Figure 3.1.
Table 3.1 List of Interrupts
Status Bit
(Interrupt Name)
Interrupt Factor
Related Item
VBUS
(Vbus Interrupt)
Change of Vbus input level
(change of "L"->"H", "H"->"L")
Confirmation of Vbus pin input state by the
Vbus bit of the Interrupt Status Register 0
RESM
(Resume Interrupt)
Change of USB bus state in suspend state
("J"->"K" or "SE0")
Confirmation of current device state by the
DVSQ bits of the Interrupt Status Register 0
SOFR
(SOF Detect Interrupt)
Receive of SOF packet
DVST
(Device State Transition
Interrupt)
Detection of USB bus reset
Detection of suspend state
Execution of "SET_ADDRESS"
Execution of "SET_CONFIGURATION"
Confirmation of current device state by the
DVSQ bits of the Interrupt Status Register 0
CTRT
(Control Transfer Stage
Transition Interrupt)
Transition of control write transfer status stage
Transition of control read transfer status stage
Completion of control transfer
Occurrence of control transfer sequence error
Completion of setup stage
Confirmation of current control transfer stage
state by the CTSQ bits of the Interrupt Status
Register 0
BEMP
(Buffer Empty / Size Over
Interrupt)
Transmit of all the data stored in the buffers at each
endpoint
Receive of packet exceeding the maximum packet size
during receiving data packet
Confirmation of endpoint number occurred the
interrupt by the EPB_EMP_OVR bits of the
Interrupt Status Register 3
INTN
(Buffer Not Ready Interrupt)
When NAK response is automatically executed because
of the buffer not ready state in the IN/OUT token of each
endpoint
Confirmation of endpoint number occurred
the interrupt by the EPB_NRDY bits of the
Interrupt Status Register 2.
INTR
(Buffer Ready Interrupt)
When each endpoint is buffer ready state
(read /write enable state)
Confirmation of endpoint number of the
occurred interrupt by the EPB_RDY bits of
the Interrupt Status Register 1.
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