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参数资料
| 型号： | M66291GP |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| 封装： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件页数： | 86/128页 |
| 文件大小： | 928K |
| 代理商： | M66291GP |
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M66291GP/HP
Rev 1.01 2004.11.01 page 58 of 122
When set to IN buffer (EPi_DIR bit = “1”)
When this bit is set to “0”, the CPU side buffer is ready to write the transmit data.
This bit is cleared to “0” due to one of the reasons as follows:
When set to single buffer mode (EPi_DBLB bit = “0”)
Completes transmitting of SIE side buffer.
Writes “1” to the SCLR bit.
Writes “1” to the ACLR bit.
When set to double buffer mode (EPi_DBLB bit = “1”)
Completes transmitting of SIE side buffer and writing of CPU side buffer.
Writes “1” to the SCLR bit.
Writes “1” to the ACLR bit.
Writes “1” to the BCLR bit.
The transmit completion is changed by the EPi_RWMD bit.
This bit is set to “1” due to one of the reasons as follows:
Completes writing the transmit data to CPU side buffer.
Writes “1” to this bit.
When “1” is written to this bit, the write operation is forcibly completed. When some written
data exists in the buffer, that data is solely transmitted as the short packet. Here, if the
buffer is empty or cleared, the zero-length packet is transmitted. The buffer can be cleared
using the BCLR bit. Further, the zero-length packet can be transmitted by writing “1”
simultaneously to this bit and to the BCLR bit. In this case the buffer is cleared by setting “1”
to BCLR bit, and this bit is cleared to “0” after the zero-length packet is transmitted.
The write completion also is changed by the EPi_RWMD bit.
(3) BCLR (Buffer Clear) Bit (b12)
This bit clears the data written to the CPU side buffer.
When set to OUT buffer (EPi_DIR bit = “0”)
When the IVAL bit is set to “1”, the following operations are executed by writing “1” to this bit:
Clears CPU side buffer.
Clears the IVAL bit of this register.
Clears the CPU_DTLN bits of this register.
When set to IN buffer (EPi_DIR bit = “1”)
When the IVAL bit is set to “0”, the following operations are executed by writing “1” to this bit:
Clears CPU side buffer.
Further, the zero-length packet can be transmitted by writing “1” simultaneously to this bit and to the
IVAL bit. For details, refer to “IVAL bit”.
This bit automatically returns to “0” after the buffer is cleared.
Note:
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
(4) Creq (CPU_FIFO Ready) Bit (b11)
When this bit is equal to “1”, this bit indicates the states as follows:
CPU_FIFO Data Register can not be accessed.
The IVAL bit value of this register is invalid.
The CPU_DTLN bit values of this register are invalid.
Make sure that this bit is equal to “0” before accessing the aforesaid registers/bits.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M66291GP#201 | 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP |
| M66291GP#RB0S | 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
| M66291GPRB0S | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48 |
| M66291HP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller) |
| M66291HP#200D | 功能描述:IC USB CONTROLLER GEN-PUR 52VQFN RoHS:否 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
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