参数资料
型号: M66291GP
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封装: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件页数: 94/128页
文件大小: 928K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 66 of 122
(9) Octl (Register 8-Bit Mode) Bit (b6)
This bit sets the access mode of the Dn_FIFO Data Register.
When this bit is set to “0”, the Dn_FIFO Data Register is set to 16-bit mode, and all bits of the Dn_FIFO Data
Register are valid.
When this bit is set to “1”, the Dn_FIFO Data Register is set to 8-bit mode, and the upper-order 8 bits of the
Dn_FIFO Data Register (b15 to b8) are invalid.
When set to OUT buffer (EPi_DIR bit = “0”), change this bit before receiving the data. When set to IN buffer
(EPi_DIR bit = “1”), if the Dreq bit is equal to “1”, do not change this bit.
This bit becomes invalid (fixed to 8-bit mode) when the mode is set to 8-bit by *HWR/*BYTE pin.
In such case, this bit is read “0”.
Note:
The access width of the Dn_FIFO Data Register is controlled by the logical sum of this bit and the EPi_Octl bits
of the EPi Configuration Register 1 specified by the DMA_EP bits. Hence, the mode is set to 8-bit if “1” is set to
either this bit or to the EPi_Octl bits of the EPi Configuration Register 1. Make sure that both bits must be set to
“0” to change to 16-bit mode.
Note:
Do not change this bit while accessing the Dn_FIFO Data Register.
(10) DMA_EP (DMA Transfer Endpoint Designate) Bits (b3~b0)
These bits select the endpoint of DMA transfer.
Make sure that the endpoint selection does not get overlapped with the selection by the CPU_EP bits.
When making a change in these bits to select the other endpoint, make sure that the source endpoint and the
destination endpoint to be changed are not under the access by the CPU/DMA or during
receiving/transmitting of SIE (under access to FIFO buffer).
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