参数资料
型号: M66291GP
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封装: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件页数: 36/128页
文件大小: 928K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 13 of 122
(3) Xtal (Clock Select) Bits (b13~b12)
These bits set the multiplication factor of the external clock into PLL.
Since it is necessary to supply 48 MHz to the core block, the setting values of these bits are determined by the
clock frequency to be input into the PLL.
Refer to Figure 2.3.
(4) SCKE (Internal Clock Enable) Bit (b11)
This bit sets the clock supply into the core block.
Set the PLLC bit to “1” and wait until the oscillation of the PLL stabilizes before setting this bit to “1”.
Refer to Figure 2.3.
O scillation
buffer
XCKE bit
PLL
External clock
PLLC bit
Enable/Disable
SCKE bit
Xtal bits
Multiplying
factor
Core block
I/O block
Enable/Disable
Figure 2.3 Clock Control
(5) USBPC (USB Transceiver Power Control) Bit (b10)
This bit sets the enable/disable of the USB transceiver block of I/O block.
Even if this bit is set to “0”, it is possible to receive the resume signal during the Suspended state (DVSQ bits
= “1xx”). It is necessary that the Tr_on bits be set to “x1” (during operation of SIE block).
(6) Tr_on (Tr_on Output Control) Bits (b9~b8)
These bits set the TrON signal output from I/O block and the enable/disable of SIE block in core block.
(7) USBE (USB Module Operation Enable) Bit (b0)
This bit sets S/W reset.
When this bit is set to “0”, the M66291 enters the S/W reset state and the registers are set to their S/W reset
state.
.
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