参数资料
型号: M66291GP
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封装: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件页数: 113/128页
文件大小: 928K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 83 of 122
3.2 FIFO Buffer
The M66291 has 6 endpoints available for bulk/interrupt/isochronous transfers in addition to endpoint 0 for
control transfer.
The M66291 is equipped with a total of 3 Kbytes FIFO that can be used as the buffer of the endpoint and can be
assigned arbitrary byte count in 64-byte unit against each endpoint.
3.2.1
FIFO Buffer Configuration
The endpoint buffer can be set for double buffer configuration and continuous transmit/receive mode. Each
buffer configuration is set by the registers as follows:
Endpoint 0:
Control Transfer Control Register
EP0 Packet Size Register
EP0_FIFO Continuous Transmit Data Length Register
Endpoint 1~6:
EPi Configuration Register 0
EPi Configuration Register 1
3.2.2
Buffer Access
The buffers of endpoints 0 to 6 can be accessed by the four data registers as follows:
<EP0_FIFO Data Register>
Quantity : 1 piece
Exclusively used for endpoint 0
<CPU_FIFO Data Register >
Quantity : 1 piece
Shared with endpoints 1 to 6 (specified by the CPU_EP bits)
<Dn_FIFO Data Register >
Quantity : 2 pieces
Shared with endpoints 1 to 6 (specified by the DMA_EP bits)
Can be accessed by DMAC
These four data registers can be set independently to 8-bit/16-bit mode by the Octl bit.
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