参数资料
型号: M66291GP
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封装: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件页数: 90/128页
文件大小: 928K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 62 of 122
(2) SCLR (Buffer Clear) Bit (b12)
This bit is valid against the endpoint set to the IN buffer (EPi_DIR bit = “1”). Do not write “1” when set to the
OUT buffer (EPi_DIR bit = “0”)
The SIE side buffer is cleared by writing “1” to this bit.
Note:
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
Note:
Make sure that the response PID is set to NAK (EPi_PID bits = “00”) and the Sreq bit to “0” before writing “1” to
this bit.
(3) Sreq (SIE_FIFO Ready) Bit (b11)
This bit indicates to enable/disable of writing to the TGL bit and SCLR bit.
When this bit is set to “1”, do not write to the TGL bit and SCLR bit.
(4) SIE_DTLN (SIE_FIFO Receive Data Length) Bits (b10~b0)
These bits are valid against the endpoint set to the OUT buffer (EPi_DIR bit = “0”) and indicates the receive
data number (byte count) in the SIE side buffer (renewed after every ACK transmit).
Note:
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
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