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参数资料
| 型号： | M66291GP |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| 封装： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件页数： | 82/128页 |
| 文件大小： | 928K |
| 代理商： | M66291GP |
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M66291GP/HP
Rev 1.01 2004.11.01 page 55 of 122
(2) RWND (Buffer Rewind) Bit (b12)
This bit rewinds (initializes) the buffer pointer.
When set to OUT buffer (EPi_DIR bit = “0”)
When the IVAL bit of the CPU_FIFO Control Register is set to “1”, the buffer reading pointer can be
initialized by writing “1” to this bit. This enables reading of the receive data from the beginning.
When set to IN buffer (EPi_DIR bit = “1”)
When the IVAL bit of the CPU_FIFO Control Register is set to “0”, the buffer writing pointer can be
initialized by writing “1” to this bit. This enables resetting of the transmit data from the beginning.
The operation is equivalent to the case when “1” is set to the BCLR bit if set to IN buffer.
(3) BSWP (Byte Swap Mode) Bit (b7)
This bit sets the endian of the CPU_FIFO Data Register.
When this bit is set to “0”, the CPU_FIFO Data Register gets such as little endian.
When this bit is set to “1”, the CPU_FIFO Data Register gets such as big endian.
b15~b8
b7~b0
Little Endian
odd number address
even number address
Big Endian
even number address
odd number address
Note:
Do not set this bit to “1” when the mode is set to 8-bit (set by the Octl bit or *HWR/*BYTE pin).
(4) Octl (Register 8-Bit Mode) Bit (b6)
This bit sets the access mode of the CPU_FIFO Data Register.
When this bit is set to “0”, the CPU_FIFO Data Register is set to 16-bit mode, and all bits of the CPU_FIFO
Data Register are valid.
When this bit is set to “1”, the CPU_FIFO Data Register is set to 8-bit mode, and the upper-order 8 bits of the
CPU_FIFO Data Register (b15 to b8) are invalid.
When set to OUT buffer (EPi_DIR bit = “0”), change this bit before receiving the data. When set to IN buffer
(EPi_DIR bit = “1”), if the Creq bit is equal to “1”, do not change this bit.
This bit becomes invalid (fixed to 8-bit mode) when the mode is set to 8-bit by *HWR/*BYTE pin.
In such case, this bit is read “0”.
Note:
The access width of the CPU_FIFO Data Register is controlled by the logical sum of this bit and the EPi_Octl
bits of the EPi Configuration Register 1 specified by the CPU_EP bits. Hence, the mode is set to 8-bit if “1” is
set to either this bit or to the EPi_Octl bits of the EPi Configuration Register 1. Make sure that both bits must be
set to “0” to change to 16-bit mode.
(5) CPU_EP (CPU Access Endpoint Designate) Bits (b3~b0)
These bits select the endpoint accessed by CPU.
Make sure that the endpoint selection does not get overlapped with the selection by the DMA_EP bits.
When making a change in these bits to select the other the endpoint, make sure that the source endpoint and
the destination endpoint to be changed are not under the access by the CPU or during receiving/transmitting
of SIE (under access to FIFO buffer).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M66291GP#201 | 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP |
| M66291GP#RB0S | 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
| M66291GPRB0S | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48 |
| M66291HP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller) |
| M66291HP#200D | 功能描述:IC USB CONTROLLER GEN-PUR 52VQFN RoHS:否 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
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