- 您现在的位置：买卖IC网 > PDF目录98008 > M66291GP UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 PDF资料下载
参数资料
| 型号： | M66291GP |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| 封装： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件页数： | 92/128页 |
| 文件大小： | 928K |
| 代理商： | M66291GP |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页当前第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页
M66291GP/HP
Rev 1.01 2004.11.01 page 64 of 122
(1) BUST (Burst Mode) Bit (b15)
When set to cycle steal transfer, the assertion and negation of the DREQ signal are repeated every time the
signal is subjected to DMA transfer (8-bit or 16-bit) when the CPU side buffer can be accessed. The negation is
executed when the Dn_FIFO Data Register is accessed.
When set to burst transfer, it keeps on asserting the DREQ signal until the reading/writing of the CPU side
buffer completes when the CPU side buffer can be accessed.
It is possible to forcibly complete the writing and then enabling transmit of short packet by asserting the TC
signal at the time of writing.
(2) DFORM (Transfer Method) Bit (b14~b13)
These bits select the DMA transfer method.
When set to “00”
At the time of reading, the data of the Dn_FIFO Data Register is available while the DACK signal is at
“L” and the read signal at “L”.
At the time of writing, the data is written to the Dn_FIFO Data Register when the DACK signal is at
“L” and by the rising edge of write signal.
When set to “01”
Only the DACK signal is used and the Read/Write signal is not used (the Read/Write signal is ignored).
At the time of reading, the data of the Dn_FIFO Data Register is available while the DACK signal is at
“L”.
At the time of writing, the data is written to the Dn_FIFO Data Register by the rising edge of DACK
signal.
When set to “10”
In place of the DACK signal (the DACK signal is ignored here), the address signal can be used to
read/write the data of the Dn_FIFO Data Register.
At the time of reading, the data of the Dn_FIFO Data Register is available when the read signal is at
“L”.
At the time of writing, the data is written to the Dn_FIFO Data Register by the rising edge of write.
When the endpoint set to the OUT buffer (EPi_DIR bit = “0”) is assigned to the DMA_EP, writing operation to
the Dn_FIFO Data Register is ignored.
Similarly, when the endpoint set to the IN buffer (EPi_DIR bit = “1”) is assigned to the DMA_EP, reading
operation to the Dn_FIFO Data Register is ignored (undefined value is read).
(3) RWND (Buffer Rewind) Bit (b12)
This bit rewinds (clears) the buffer pointer.
When set to OUT buffer (EPi_DIR bit = “0”)
When the IVAL bit of the Dn_FIFO Control Register is set to “1”, the buffer reading pointer can be
cleared by writing “1” to this bit. This enables reading of the receive data from the beginning.
When set to IN buffer (EPi_DIR bit = “1”)
When the IVAL bit of the Dn_FIFO Control Register is set to “0”, the buffer writing pointer can be
cleared by writing “1” to this bit. This enables resetting of the transmit data from the beginning.
(4) ACKA (DACK Polarity) Bit (b11)
This bit sets the DACK signal polarity.
(5) REQA (DREQ Polarity) Bit (b10)
This bit sets the DREQ signal polarity.
相关PDF资料 |
PDF描述 |
|---|---|
| M68HC08AZ0 | 8-BIT, EEPROM, 8 MHz, MICROCONTROLLER, PQFP100 |
| M69030 | GRAPHICS PROCESSOR, PBGA278 |
| MA4T85633 | C BAND, Si, NPN, RF SMALL SIGNAL TRANSISTOR |
| MA4T85600 | Si, RF POWER TRANSISTOR |
| MA4T85635 | C BAND, Si, NPN, RF SMALL SIGNAL TRANSISTOR |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M66291GP#201 | 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP |
| M66291GP#RB0S | 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
| M66291GPRB0S | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48 |
| M66291HP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller) |
| M66291HP#200D | 功能描述:IC USB CONTROLLER GEN-PUR 52VQFN RoHS:否 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
发布紧急采购，3分钟左右您将得到回复。