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参数资料
| 型号： | M66291GP |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| 封装： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件页数： | 84/128页 |
| 文件大小： | 928K |
| 代理商： | M66291GP |
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M66291GP/HP
Rev 1.01 2004.11.01 page 57 of 122
(1) IDLY (Isochronous Transmit Delay Set) Bit (b14)
In isochronous transfer, transmission can be started by writing “1” to this bit or to the IVAL bit after writing
the transmit data to the buffer (Note).
When “1” is written to this bit, the data is transmitted by receiving the IN token after confirming the received
SOF packet. After the data transmit starts, this is cleared to “0” (Refer to Figure 2.11).
When “1” is written to the IVAL bit of this register, the data is transmitted by receiving the next IN token
(Refer to Figure 2.12).
Note:
Set the transmit data size + 1 byte or more to the EPi_MXPS bits. When set to transmit data size, the IVAL bit is
set to “1” when the writing to the buffer completes. Hence, this function is not applicable when set to 1023
bytes, the maximum value of the EPi_MXPS bits.
Flame #m
SO F
Flame #(m+1)
IN
ID LY="1" set
SO F
IN
T ransmit start
Figure 2.11 Transmit start timing at IDLY bit = “1”
Flame #m
SO F
IN
IVAL="1" set
T ransmit start
Figure 2.12 Transmit start timing at IVAL bit = “1”
(2) IVAL (IN Buffer Set/OUT Buffer Status) Bit (b13)
This bit indicates valid value when the Creq bit of this register is equal to “0”.
This bit sets/clears the EPB_RDY bit to “1” (Refer to “EPB_RDY bit”).
When set to OUT buffer (EPi_DIR bit = “0”)
When this bit is set to “1”, the receive data in the CPU side buffer is ready to be read.
This bit is set to “1” due to one of the reasons as follows:
When set to single buffer mode (EPi_DBLB bit = “0”)
Completes receiving (SIE side buffer).
Writes “1” to the TGL bit.
When set to double buffer mode (EPi_DBLB bit = “1”)
Completes receiving of SIE side buffer and reading of CPU side buffer.
Writes “1” to the TGL bit.
The receive completion is changed by the EPi_RWMD bit.
This bit is cleared to “0” due to one of the reasons as follows:
Reads out all the receive data in the CPU side buffer.
Writes “1” to the BCLR bit.
Writes “1” to the ACLR bit.
Note:
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M66291GP#201 | 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP |
| M66291GP#RB0S | 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
| M66291GPRB0S | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48 |
| M66291HP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller) |
| M66291HP#200D | 功能描述:IC USB CONTROLLER GEN-PUR 52VQFN RoHS:否 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
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