参数资料
型号: M66291GP
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封装: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件页数: 116/128页
文件大小: 928K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 86 of 122
3.2.4
IVAL Bit and EPB_RDY Bit
The IVAL bit is available per endpoint.
These IVAL bits can be specified by the CPU_EP bits and the DMA_EP bits, and the read/write is possible by
the IVAL bit of the CPU_FIFO Control Register and the IVAL bit of the Dn_FIFO Control Register.
The EPB_RDY bit can be set/cleared by the IVAL bit at each endpoint, irrespective of the aforesaid setting.
Similarly, the EPB_NRDY bit and EPB_EMP_OVR bit can be set/cleared regardless of the CPU_EP
bit/DMA_EP bit.
Make sure that the “1” setting to the EPB_RDY bit of the endpoint specified by the DMA_EP bit changes
according to the setting of the INTM bit.
EP0_FIFO Data Register
(EP0_FIFO Control Register)
Endpoint 0
IVAL
IVAL bit
CPU_FIFO Data Register
(CPU_FIFO Control Register)
Endpoint 1
IVAL
IVAL bit
Endpoint 2
IVAL
Endpoint 3
IVAL
Designates by C PU_EP bit
Endpoint i
IVAL
D0_FIFO Data Register
(D0_FIFO Control Register)
IVAL bit
D1_FIFO Data Register
(D1_FIFO Control Register)
IVAL bit
Dn_FIFO Data Register
(Dn_FIFO Control Register)
IVAL bit
Designates by DMA_EP bit
Interrupt Status Register1 (EPB_RDY)
Interrupt Status Register2 (EPB_NRDY)
Interrupt Status Register 3 (EPB_EMP_O VR)
FIFO Status Register (EPB_ST S)
Fix
Figure 3.4 IVAL Bit and EPB_RDY Bit
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