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参数资料
型号： MC68HC05V7FN
厂商： MOTOROLA INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC68
封装： PLASTIC, LCC-68
文件页数： 109/170页
文件大小： 589K
代理商： MC68HC05V7FN
SECTION 5: INTERRUPTS
MOTOROLA
Page 29
MC68HC05V7 Specification Rev. 1.0
SECTION 5
INTERRUPTS
The MCU can be interrupted seven different ways:
1. Nonmaskable Software Interrupt Instruction (SWI)
2. External Asynchronous Interrupt (IRQ)
3. External Interrupt via IRQ on PA0-PA7, PC0-PC7
4. Internal 16-bit Timer Interrupt (TIMER)
5. Internal Serial Peripheral Interface Interrupt (SPI)
6. Internal MDLC Interrupt (MDLC)
7. Internal 8-bit Timer Interrupt
5.1
CPU INTERRUPT PROCESSING
Interrupts cause the processor to save register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware interrupts do not
cause the current instruction execution to be halted, but are considered pending until the
current instruction is complete.
If interrupts are not masked (I-bit in the CCR is clear) and the corresponding interrupt
enable bit is set the processor will proceed with interrupt processing. Otherwise, the next
instruction is fetched and executed. If an interrupt occurs the processor completes the
current instruction, then stacks the current CPU register states, sets the I-bit to inhibit
further interrupts, and finally checks the pending hardware interrupts. If more than one
interrupt is pending following the stacking operation, the interrupt with the highest vector
location shown in Table 5-1 will be serviced first. The SWI is executed the same as any
other instruction, regardless of the I-bit state.
When an interrupt is to be processed the CPU fetches the address of the appropriate
interrupt software service routine from the vector table at locations $3FF2 thru $3FFF as
defined in Table 5-1.
Table 5-1:
Vector Address for Interrupts and Reset
Register
N/A
TSR
MSR
SPSR
CTCSR
Flag
Name
N/A
OCF,ICF,TOF
TXMS,RXMS
SPIF
TOFE,RTIE
Interrupts
Reset
Software
External Interrupts **
16-bit Timer Interrupts
MDLC Interrupt
SPI Interrupt
8 bit Timer Interrupts
CPU
Interrupt
RESET
SWI
IRQ
TIMER
MDLC
SPI
TIMER,RTI
Vector Address
$3FFE-$3FFF
$3FFC-$3FFD
$3FFA-$3FFB
$3FF8-$3FF9
$3FF6-$3FF7
$3FF4-$3FF5
$3FF2-$3FF3
** External interrupts include IRQ, PORTA and PORTC sources
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